公开(公告)号：US08796833B2

公开(公告)日：2014-08-05

申请号：US13572302

申请日：2012-08-10

申请人： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

发明人： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC分类号： H01L23/495

摘要： A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

公开(公告)号：US08779588B2

公开(公告)日：2014-07-15

申请号：US13427753

申请日：2012-03-22

申请人： Chen-Hua Yu ,  Jing-Cheng Lin

发明人： Chen-Hua Yu ,  Jing-Cheng Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13564 ,  H01L2224/1412 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/381

摘要： The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package.

摘要翻译： 用于形成描述的多芯片封装的机构使得具有不同凸块尺寸的芯片被封装到公共衬底。 具有较大凸块的芯片可以与衬底上的两个或更多个更小的凸块接合。 相反，芯片上的两个或更多个小凸块可以与基板上的大凸块粘合。 通过允许具有不同尺寸的凸块结合在一起，具有不同凸块尺寸的芯片可以封装在一起以形成多芯片封装。

公开(公告)号：US08772929B2

公开(公告)日：2014-07-08

申请号：US13297992

申请日：2011-11-16

申请人： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

发明人： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

摘要： A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

摘要翻译： 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。

公开(公告)号：US08703542B2

公开(公告)日：2014-04-22

申请号：US13539229

申请日：2012-06-29

申请人： Jing-Cheng Lin ,  Jui-Pin Hung

发明人： Jing-Cheng Lin ,  Jui-Pin Hung

IPC分类号： H01L21/50

CPC分类号： H01L24/10 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/82001 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

摘要： The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

摘要翻译： 上述晶片级封装（WLP）的机理的实施例利用平坦化停止层来确定形成再分配线（RDL）之前除去过量模塑料的终点。 WLP的这种机制被用于实现扇出和多芯片封装。 这些机构还可用于制造包括具有不同类型的外部连接的芯片（或模具）的包装。 例如，具有预先形成的凸块的模具可以与模具封装而没有预先形成的凸块。

公开(公告)号：US08567837B2

公开(公告)日：2013-10-29

申请号：US12954180

申请日：2010-11-24

申请人： Hsin Chang ,  Hsin-Yu Chen ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Hsin Chang ,  Hsin-Yu Chen ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B66F19/00

CPC分类号： H01L21/6875 ,  B65G47/90 ,  H01L21/68707 ,  Y10T74/20305

摘要： An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports.

公开(公告)号：US08540506B2

公开(公告)日：2013-09-24

申请号：US12857245

申请日：2010-08-16

申请人： Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/67126 ,  H01L23/3121 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

摘要： A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer.

公开(公告)号：US20130115854A1

公开(公告)日：2013-05-09

申请号：US13290879

申请日：2011-11-07

申请人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B24B49/10

CPC分类号： H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

摘要翻译： 执行磨削的方法包括：选择用于晶片研磨工艺的目标轮加载，以及对晶片进行研磨处理。 随着研磨过程的进行，测量研磨过程的轮载荷。 在达到目标轮加载后停止研磨过程。 该方法或者包括选择晶片研磨过程的目标反射率，以及对晶片进行研磨处理。 随着研磨过程的进行，测量从晶片表面反射的光的反射率。 在一个反射率达到目标反射率之后停止研磨过程。

公开(公告)号：US08395221B2

公开(公告)日：2013-03-12

申请号：US12854638

申请日：2010-08-11

申请人： Jing-Cheng Lin ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chen-Hua Yu

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

摘要： A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

摘要翻译： 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。

公开(公告)号：US08361842B2

公开(公告)日：2013-01-29

申请号：US12880736

申请日：2010-09-13

申请人： Chen-Hua Yu ,  Jing-Cheng Lin

发明人： Chen-Hua Yu ,  Jing-Cheng Lin

IPC分类号： H01L21/50

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L21/568 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/13 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

摘要翻译： 一种方法包括提供载体上设置有粘合层; 以及提供包括第一表面，与第一表面相对的第二表面的模具。 模具还包括与第二表面相邻的多个接合焊盘; 以及多个接合焊盘上的介电层。 该方法还包括将模具放置在粘合剂层上，其中第一表面面向粘合剂层，电介质层背向粘合剂层; 形成模塑料以覆盖模具，其中模塑料围绕模具; 将模塑料的一部分直接在模具上去除以暴露介电层; 以及在所述模制化合物上形成再分配线，并通过所述介电层电耦合到所述多个键合焊盘之一。

公开(公告)号：US20130020698A1

公开(公告)日：2013-01-24

申请号：US13189127

申请日：2011-07-22

申请人： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

摘要： A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

摘要翻译： 提供了一种用于导电柱的系统和方法。 一个实施例包括具有位于其外边缘周围的沟槽的导电柱。 当在导电柱上形成导电凸块时，沟槽用于引导诸如焊料的导电材料。 导电柱然后可以通过导电材料电连接到另一接触件。