公开(公告)号：US09978788B2

公开(公告)日：2018-05-22

申请号：US15006052

申请日：2016-01-25

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chi-Chang Liao

IPC: H01J40/14 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/16

Abstract: A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.

公开(公告)号：US09947716B2

公开(公告)日：2018-04-17

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chien-Min Lin

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US09887229B2

公开(公告)日：2018-02-06

申请号：US15226327

申请日：2016-08-02

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

公开(公告)号：US09875912B2

公开(公告)日：2018-01-23

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  G06K9/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

公开(公告)号：US09425134B2

公开(公告)日：2016-08-23

申请号：US14339323

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  G06K9/00 ,  H01L25/065 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09406590B2

公开(公告)日：2016-08-02

申请号：US14255883

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Yen-Shih Ho ,  Tsang-Yu Liu

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/494 ,  H01L2224/8536 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和接合焊盘。 半导体芯片具有设置在下表面上的第一导电焊盘和对应于第一导电焊盘的第一孔。 第一孔和隔离层从上表面延伸到下表面以暴露第一导电垫。 再分布金属层设置在隔离层上并具有对应于第一导电焊盘的再分布金属线，再分布金属线通过开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘以将第一导电焊盘电连接到接合焊盘。 还提供了其方法。

公开(公告)号：US09331256B2

公开(公告)日：2016-05-03

申请号：US14464570

申请日：2014-08-20

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Chia-Sheng Lin ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L21/76 ,  H01L27/146 ,  H01L33/62 ,  H01L21/768

CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

公开(公告)号：US09331024B2

公开(公告)日：2016-05-03

申请号：US14092795

申请日：2013-11-27

Applicant: XINTEC INC.

Inventor： Yao-Hsiang Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Shu-Ming Chang

IPC: H01L23/552 ,  H01L21/71 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/71 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06155 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract translation: IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于 封装层的注入，以及形成在绝缘层的顶表面上并与用于电磁屏蔽的集成电路层的焊盘电隔离的电磁屏蔽层。 因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。 此外，通孔的设计有助于进一步的包装过程。

公开(公告)号：US08779558B2

公开(公告)日：2014-07-15

申请号：US13829802

申请日：2013-03-14

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US10461117B2

公开(公告)日：2019-10-29

申请号：US15848600

申请日：2017-12-20

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC: H01L27/146 ,  H01L21/683 ,  H01L23/00

Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.