公开(公告)号：US10161035B2

公开(公告)日：2018-12-25

申请号：US15016870

申请日：2016-02-05

Applicant: Applied Materials, Inc.

Inventor： Juan Carlos Rocha-Alvarez ,  Amit Kumar Bansal ,  Ganesh Balasubramanian ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan

IPC: C23C16/44 ,  C23C16/455 ,  F27D7/02 ,  F27D7/06 ,  H01J37/32

Abstract: A processing chamber is described having a gas evacuation flow path from the center to the edge of the chamber. Purge gas is introduced at an opening around a support shaft that supports a heater plate. A shaft wall around the opening directs the purge gas along the support shaft to an evacuation plenum. Gas flows from the evacuation plenum through an opening in a second plate near the shaft wall and along the chamber bottom to an opening coupled to a vacuum source. Purge gas is also directed to the slit valve.

公开(公告)号：US10100408B2

公开(公告)日：2018-10-16

申请号：US14594296

申请日：2015-01-12

Applicant: Applied Materials, Inc.

Inventor： Sungwon Ha ,  Kwangduk Douglas Lee ,  Ganesh Balasubramanian ,  Juan Carlos Rocha-Alvarez ,  Martin Jay Seamons ,  Ziqing Duan ,  Zheng John Ye ,  Bok Hoen Kim ,  Lei Jing ,  Ngoc Le ,  Ndanka Mukuti

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/458 ,  C23C16/509 ,  H01J37/32

Abstract: Embodiments described herein relate to a faceplate for improving film uniformity. A semiconductor processing apparatus includes a pedestal, an edge ring and a faceplate having distinct regions with differing hole densities. The faceplate has an inner region and an outer region which surrounds the inner region. The inner region has a greater density of holes formed therethrough when compared to the outer region. The inner region is sized to correspond with a substrate being processed while the outer region is sized to correspond with the edge ring.

公开(公告)号：US09837265B2

公开(公告)日：2017-12-05

申请号：US15192732

申请日：2016-06-24

Applicant: Applied Materials, Inc.

Inventor： Prashant Kumar Kulshreshtha ,  Sudha Rathi ,  Praket P. Jha ,  Saptarshi Basu ,  Kwangduk Douglas Lee ,  Martin J. Seamons ,  Bok Hoen Kim ,  Ganesh Balasubramanian ,  Ziqing Duan ,  Lei Jing ,  Mandar B. Pandit

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  H01L21/033 ,  H01L21/66 ,  C23C16/26 ,  C23C16/04 ,  H01L21/311

CPC classification number: H01L21/02274 ,  C23C16/04 ,  C23C16/26 ,  C23C16/455 ,  C23C16/45502 ,  C23C16/45508 ,  C23C16/45565 ,  C23C16/458 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/46 ,  H01L21/02115 ,  H01L21/0337 ,  H01L21/31144 ,  H01L22/12

Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.

公开(公告)号：US09816187B2

公开(公告)日：2017-11-14

申请号：US15278455

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Wenyoung Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik ,  Ganesh Balasubramanian

IPC: G01N21/00 ,  C23C16/52 ,  G01B11/06 ,  H01L21/00 ,  H01L21/687 ,  H01L21/67 ,  C23C16/509 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  G01N21/55 ,  G01N21/65 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/45565 ,  C23C16/4557 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  G01N2201/1222 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

公开(公告)号：US20160240410A1

公开(公告)日：2016-08-18

申请号：US15139274

申请日：2016-04-26

Applicant: Applied Materials, Inc.

Inventor： Paul B. Reuter ,  Ganesh Balasubramanian ,  JuanCarlos Rocha-Alvarez ,  Jeffrey B. Robinson ,  Dale Robert du Bois ,  Paul Connors

IPC: H01L21/67 ,  H01L21/673 ,  H01L21/677

CPC classification number: H01L21/67178 ,  H01L21/67103 ,  H01L21/6719 ,  H01L21/67201 ,  H01L21/67313 ,  H01L21/67712 ,  Y10T29/49998

Abstract: A substrate lift assembly is disclosed. The substrate lift assembly includes a lift frame, a plurality of fingers extending from the frame, the fingers adapted to support a substrate, and a containment ring supported by the lift frame. Process load locks including the substrate lift assembly are disclosed, as are other aspects.

Abstract translation: 公开了一种基板升降组件。 基板升降组件包括升降架，从框架延伸的多个指状物，适于支撑基板的指状物以及由升降机架支撑的收容环。 与其他方面一样，公开了包括基板升降组件的过程负载锁定。

公开(公告)号：US09157730B2

公开(公告)日：2015-10-13

申请号：US14056203

申请日：2013-10-17

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Ganesh Balasubramanian ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik

IPC: G01B11/06 ,  H01L21/00

CPC classification number: C23C16/52 ,  C23C16/45565 ,  C23C16/4557 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  G01N2201/1222 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

Abstract translation: 描述了根据PECVD工艺处理衬底的方法。 调整衬底的温度分布以改变衬底上的沉积速率分布。 调整等离子体密度分布以改变跨衬底的沉积速率分布。 暴露于等离子体的室表面被加热以改善等离子体密度均匀性并减少在室表面上形成低质量的沉积物。 原位计量可用于监测沉积过程的进展并触发涉及衬底温度曲线，等离子体密度分布，压力，温度和反应物流动的控制动作。

公开(公告)号：US11898249B2

公开(公告)日：2024-02-13

申请号：US18108989

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Wenyoung Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward W. Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik ,  Ganesh Balasubramanian

IPC: C23C16/52 ,  G01B11/06 ,  H01L21/687 ,  H01L21/67 ,  C23C16/509 ,  G01N21/55 ,  G01N21/65 ,  H01L21/00 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/458 ,  C23C16/4557 ,  C23C16/45565 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687 ,  G01N2201/1222

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

公开(公告)号：US20230411462A1

公开(公告)日：2023-12-21

申请号：US18460290

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Akhil Singhal ,  Allison Yau ,  Sang-Jin Kim ,  Zeqiong Zhao ,  Zhijun Jiang ,  Deenesh Padhi ,  Ganesh Balasubramanian

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/40114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L29/42324

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

公开(公告)号：US11721545B2

公开(公告)日：2023-08-08

申请号：US17035107

申请日：2020-09-28

Applicant: Applied Materials, Inc.

Inventor： Anup Kumar Singh ,  Rick Kustra ,  Vinayak Vishwanath Hassan ,  Bhaskar Kumar ,  Krishna Nittala ,  Pramit Manna ,  Kaushik Comandoor Alayavalli ,  Ganesh Balasubramanian

IPC: H01L21/02 ,  H01L21/033 ,  H01J37/32 ,  B08B7/00 ,  C23C16/505 ,  C23C16/26 ,  C23C16/44

CPC classification number: H01L21/02274 ,  B08B7/0035 ,  C23C16/26 ,  C23C16/4405 ,  C23C16/505 ,  H01J37/3244 ,  H01J37/32082 ,  H01J37/32862 ,  H01L21/02115 ,  H01L21/0332

Abstract: Embodiments of the present disclosure generally relate to methods of depositing carbon film layers greater than 3,000 Å in thickness over a substrate and surface of a lid of a chamber using dual frequency, top, sidewall and bottom sources. The method includes introducing a gas to a processing volume of a chamber. A first radiofrequency (RF) power is provided having a first frequency of about 40 MHz or greater to a lid of the chamber. A second RF power is provided having a second frequency to a bias electrode disposed in a substrate support within the processing volume. The second frequency is about 10 MHz to about 40 MHz. An additional third RF power is provided having lower frequency of about 400 kHz to about 2 MHz to the bias electrode.

公开(公告)号：US20230205196A1

公开(公告)日：2023-06-29

申请号：US18114915

申请日：2023-02-27

Applicant: Applied Materials, Inc.

Inventor： Sidharth Bhatia ,  Garrett H. Sin ,  Heng-Cheng Pai ,  Pramod Nambiar ,  Ganesh Balasubramanian ,  Irfan Jamil

IPC: G05B23/02 ,  G05B19/418 ,  G06F11/34 ,  G06F11/30 ,  G05B19/404

CPC classification number: G05B23/0286 ,  G05B19/404 ,  G05B19/4183 ,  G05B19/4184 ,  G05B19/41875 ,  G05B19/41885 ,  G05B23/024 ,  G05B23/0294 ,  G06F11/3089 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3495 ,  G06N20/00

Abstract: A method includes identifying sets of sensor data associated with wafers processed via wafer processing equipment and identifying sets of metrology data associated with the wafers processed via the wafer processing equipment. The method further includes generating sets of aggregated sensor-metrology data, each of the sets of aggregated sensor-metrology data including a respective set of sensor data and a respective set of metrology data. The method further includes causing, based on the sets of aggregated sensor-metrology data, performance of a corrective action associated with the wafer processing equipment.