公开(公告)号：US07375021B2

公开(公告)日：2008-05-20

申请号：US11308539

申请日：2006-04-04

申请人： Daniel C. Edelstein ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. Melville

发明人： Daniel C. Edelstein ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. Melville

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

摘要： A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

摘要翻译： 用于远端（FBEOL）半导体器件形成的方法包括在半导体晶片的上层形成端子铜焊盘，在端子铜焊盘上形成绝缘堆叠，以及在端部铜焊盘的一部分内图案化和打开端子通孔 绝缘堆叠，以便留下保护端子铜焊盘的绝缘堆叠的底盖层。 在绝缘堆叠的顶部上形成并图案化有机钝化层，并且去除端子铜焊盘上的底盖层。 球限制冶金（BLM）堆叠沉积在有机钝化层和端子铜焊盘上，并且在BLM堆叠的图案化部分上形成焊球连接。

公开(公告)号：US07348270B1

公开(公告)日：2008-03-25

申请号：US11625449

申请日：2007-01-22

申请人： David H. Danovitch ,  Mukta G. Farooq ,  Peter A. Gruber ,  John U. Knickerbocker ,  George R. Proto ,  Da-Yuan Shih

发明人： David H. Danovitch ,  Mukta G. Farooq ,  Peter A. Gruber ,  John U. Knickerbocker ,  George R. Proto ,  Da-Yuan Shih

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L21/6835 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/27334 ,  H01L2224/73104 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.

摘要翻译： 用于在晶片的附接点上形成互连的方法包括以下步骤：提供具有预定形状的多个空腔的模具，在空腔的表面上沉积脱模剂，用互连材料填充空腔以形成互连， 从模具中除去脱模剂，以及将互连件附接到晶片的附接点。 除了剥离层之外，还可任选地沉积粘合剂层。 粘合剂层可以用于例如将芯片粘合到包装上。

公开(公告)号：US20080017984A1

公开(公告)日：2008-01-24

申请号：US11459119

申请日：2006-07-21

申请人： Mukta G. Farooq ,  Tien-Jen Cheng ,  Roger A. Quon

发明人： Mukta G. Farooq ,  Tien-Jen Cheng ,  Roger A. Quon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.

摘要翻译： 提供微电子元件及其制造方法。 微电子元件包括覆盖衬底的主表面的接触焊盘。 接触垫在接触表面具有包含铜的组成。 还提供覆盖在基底的主表面上的钝化层。 钝化层覆盖接触焊盘，使得其暴露接触表面的至少一部分。 布置在堆叠中的多个金属层覆盖在接触表面和钝化层的至少一部分上。 堆叠包括多层，其可以具有不同的厚度和不同的金属，其中最低层包括与接触表面接触的钛（Ti）和镍（Ni）。

公开(公告)号：US07281667B2

公开(公告)日：2007-10-16

申请号：US10907761

申请日：2005-04-14

申请人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

发明人： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC分类号： G06K19/06

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US07079393B2

公开(公告)日：2006-07-18

申请号：US10904555

申请日：2004-11-16

申请人： Evan G. Colgan ,  Frank L. Pompeo ,  Glenn G. Daves ,  Hilton T. Toy ,  Bruce K. Furman ,  David L. Edwards ,  Michael A. Gaynes ,  Mukta G. Farooq ,  Sung K. Kang ,  Steven P. Ostrander ,  Jaimal M. Williamson ,  Da-Yuan Shih ,  Donald W. Henderson

发明人： Evan G. Colgan ,  Frank L. Pompeo ,  Glenn G. Daves ,  Hilton T. Toy ,  Bruce K. Furman ,  David L. Edwards ,  Michael A. Gaynes ,  Mukta G. Farooq ,  Sung K. Kang ,  Steven P. Ostrander ,  Jaimal M. Williamson ,  Da-Yuan Shih ,  Donald W. Henderson

IPC分类号： H05K7/20

CPC分类号： H01L23/4735 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A cooling system for an electronic component on a component carrier is provided. The system includes a frame, a spray manifold, and a sealing member. The frame has an opening and is connectable to the component carrier so that an annular area is defined between the opening and the electronic component. The spray manifold is sealed over the opening to define a spray area over a back surface of the electronic component. The spray manifold sprays a cooling fluid on the back surface. The sealing member seals the annular region so that input/output connectors on the component carrier are isolated from the cooling fluid.

摘要翻译： 提供了一种用于组件载体上的电子部件的冷却系统。 该系统包括框架，喷雾歧管和密封构件。 框架具有开口并且可连接到部件载体，使得在开口和电子部件之间限定环形区域。 喷雾歧管被密封在开口上以限定电子部件的后表面上方的喷射区域。 喷雾歧管在后表面喷洒冷却液。 密封构件密封环形区域，使得部件载体上的输入/输出连接器与冷却流体隔离。

公开(公告)号：US06854636B2

公开(公告)日：2005-02-15

申请号：US10314498

申请日：2002-12-06

申请人： Mukta G. Farooq ,  Mario Interrante ,  William Sablinski

发明人： Mukta G. Farooq ,  Mario Interrante ,  William Sablinski

IPC分类号： B23K35/26 ,  C22C13/00 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  B23K31/00

CPC分类号： H01L21/6835 ,  B23K35/262 ,  B23K2101/40 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

摘要翻译： 具有焊料互连液相线温度层级的电子封装，以在随后的第二级连接/组装和返工操作期间限制C4焊料互连的熔化程度。 焊料层次采用对于C4第一级焊料互连使用具有较高液相线温度的Sn / Ag和Sn / Cu的非共晶焊料合金，以及用于第二级互连的较低液相线温度合金。 当第二级芯片载体与PCB连接/组装操作发生时，芯片到芯片载体C4互连不会完全熔化。 与完全熔融的合金相比，它们仍然具有一定比例的固体和较低部分的液体。 这提供了焊料接合的减小的膨胀，并因此降低了C4互连上的较低应力。

公开(公告)号：US08970041B2

公开(公告)日：2015-03-03

申请号：US13470379

申请日：2012-05-14

申请人： Mukta G. Farooq ,  John A. Fitzsimmons

发明人： Mukta G. Farooq ,  John A. Fitzsimmons

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29014 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

摘要翻译： 组件可以包括微电子元件，例如具有其中制造的电路和半导体器件的半导体元件，以及多个电连接器，例如附接到微电子元件的触点的焊球。 连接器可以被可压缩介电材料的第一内部区域200和介电材料的第二外部区域包围。 在一个实施例中，底部填充物可以在相应的连接器或第二区域之间接触微电子元件的面。 第二区域可以提供约束力，使得在连接器的体积膨胀期间，第一区域可以抵抗第二区域的约束力而被压缩。

公开(公告)号：US08962448B2

公开(公告)日：2015-02-24

申请号：US13572004

申请日：2012-08-10

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/46

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

摘要翻译： 提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

公开(公告)号：US08692246B2

公开(公告)日：2014-04-08

申请号：US13233085

申请日：2011-09-15

申请人： Bhavana Bhoovaraghan ,  Mukta G. Farooq ,  Emily R. Kinser ,  Sudesh Saroop

发明人： Bhavana Bhoovaraghan ,  Mukta G. Farooq ,  Emily R. Kinser ,  Sudesh Saroop

IPC分类号： H01L23/58 ,  H01L29/10 ,  G01R31/26 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L23/481 ,  H01L23/58 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.

摘要翻译： 一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。 泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。 还包括测试半导体衬底的方法。

公开(公告)号：US08613996B2

公开(公告)日：2013-12-24

申请号：US12603002

申请日：2009-10-21

申请人： Mukta G. Farooq ,  Thomas F. Houghton ,  Nitin Parbhoo ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Thomas F. Houghton ,  Nitin Parbhoo ,  Richard P. Volant

IPC分类号： B32B7/00

CPC分类号： B32B37/1292 ,  B32B3/02 ,  B32B27/08 ,  B32B37/1284 ,  B32B2457/14 ,  H01L21/187 ,  Y10T156/10 ,  Y10T156/1064 ,  Y10T428/215 ,  Y10T428/219 ,  Y10T428/24355 ,  Y10T428/24752 ,  Y10T428/24777 ,  Y10T428/24802 ,  Y10T428/24851

摘要： A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.

摘要翻译： 在接合之前，将待结合的两个基板中的至少一个的外围区域上施加一层聚合物材料。 由此形成的接合结构包括第一基板，与第一基板直接接触的第二基板，以及在第一界面处与第一基板直接接触并与第二基板直接接触的聚合物材料的环。 聚合物材料环横向包围并密封第一基底与第二基底接触的界面。 可以在聚合物环内形成环形空腔。 或者，第一界面和第二界面可以相邻，而在第一和第二基板之间没有环形腔。