公开(公告)号：US20240147718A1

公开(公告)日：2024-05-02

申请号：US18406592

申请日：2024-01-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC分类号： H10B41/50 ,  H01L21/033 ,  H01L21/28 ,  H01L21/308 ,  H01L21/321 ,  H01L29/423 ,  H01L29/51 ,  H10B41/10 ,  H10B41/41

CPC分类号： H10B41/50 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3212 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/518 ,  H10B41/10 ,  H10B41/41 ,  H10B43/35

摘要： Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.

公开(公告)号：US20240145595A1

公开(公告)日：2024-05-02

申请号：US17975332

申请日：2022-10-27

申请人： Tokyo Electron Limited

发明人： H. Jim Fulford ,  Mark I. Gardner

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/51

CPC分类号： H01L29/785 ,  H01L29/0665 ,  H01L29/517

摘要： A semiconductor structure includes semiconductor layers stacked vertically over a substrate. The structure includes a gate structure interleaved with the semiconductor layers, where the gate structure wraps around a first end portion of each semiconductor layer. The structure includes dielectric layers stacked vertically over the substrate and interleaved with the semiconductor layers, where a first end portion of each dielectric layer is aligned with a second end portion of each semiconductor layer, which is laterally opposite to the first end portion of each semiconductor layer. The structure includes a metal contact extending vertically to contact the second end portion of each semiconductor layer.

公开(公告)号：US11973123B2

公开(公告)日：2024-04-30

申请号：US17578177

申请日：2022-01-18

申请人： SANDISK TECHNOLOGIES LLC

发明人： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Kartik Sondhi

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

CPC分类号： H01L29/516 ,  H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/30

摘要： A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US11973119B2

公开(公告)日：2024-04-30

申请号：US17222534

申请日：2021-04-05

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tadashi Yamaguchi

IPC分类号： H01L21/28 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC分类号： H01L29/40111 ,  G11C11/223 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30 ,  H01L29/517

摘要： A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

公开(公告)号：US11961896B2

公开(公告)日：2024-04-16

申请号：US17474879

申请日：2021-09-14

申请人： Honeywell Federal Manufacturing & Technologies, LLC

发明人： Erik Joseph Timpson ,  Justin M. Schlitzer ,  Thomas Matthew Selter ,  Michael Walsh

IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L29/84 ,  H01L29/868

CPC分类号： H01L29/51 ,  H01L29/4916 ,  H01L29/84 ,  H01L29/868

摘要： Systems and methods for building passive and active electronics with diamond-like carbon (DLC) coatings are provided herein. DLC may be layered upon substrates to form various components of electronic devices. Passive components such as resistors, capacitors, and inductors may be built using DLC as a dielectric or as an insulating layer. Active components such as diodes and transistors may be built with the DLC acting substantially like a semiconductor. The amount of sp2 and sp3 bonded carbon atoms may be varied to modify the properties of the DLC for various electronic components.

公开(公告)号：US11956968B2

公开(公告)日：2024-04-09

申请号：US17884578

申请日：2022-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-I Wu ,  Yu-Ming Lin ,  Sai-Hooi Yeong ,  Han-Jong Chia

IPC分类号： H10B51/10 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

CPC分类号： H10B51/10 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66666 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

摘要： Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

公开(公告)号：US11955532B2

公开(公告)日：2024-04-09

申请号：US17080713

申请日：2020-10-26

申请人： Intel Corporation

发明人： Jeffrey S. Leib ,  Jenny Hu ,  Anindya Dasgupta ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

摘要： Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240105520A1

公开(公告)日：2024-03-28

申请号：US18534219

申请日：2023-12-08

申请人： Intel Corporation

发明人： Anthony ST. AMOUR ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L21/8234 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/823475 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/7854 ,  H10B10/12

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US11943924B2

公开(公告)日：2024-03-26

申请号：US17181901

申请日：2021-02-22

申请人： Micron Technology, Inc.

发明人： Chris M. Carlson

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/512 ,  H10B43/35

摘要： Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.