公开(公告)号：US20170323682A1

公开(公告)日：2017-11-09

申请号：US15660552

申请日：2017-07-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: G11C16/08 ,  G11C7/10 ,  H01L25/18 ,  G11C16/04 ,  H01L25/065 ,  H01L23/00

CPC classification number: G11C16/08 ,  G11C7/1045 ,  G11C7/1057 ,  G11C16/04 ,  G11C2207/105 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.

公开(公告)号：US20170269662A1

公开(公告)日：2017-09-21

申请号：US15610612

申请日：2017-05-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Anh Ly ,  Hung Quoc Nguyen

IPC: G06F1/26 ,  G11C16/30 ,  H03K19/0185 ,  G06F1/28 ,  G11C5/14 ,  G11C7/20

CPC classification number: G06F1/266 ,  G06F1/28 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/4074 ,  G11C16/30 ,  H03K19/018521

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed.

公开(公告)号：US09673208B2

公开(公告)日：2017-06-06

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Chien-Sheng Su ,  Feng Zhou ,  Xian Liu ,  Nhan Do ,  Prateep Tuntasood ,  Parviz Ghazavi

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/11531

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

公开(公告)号：US09672930B2

公开(公告)日：2017-06-06

申请号：US14726124

申请日：2015-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Viet Tan Nguyen

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C8/10 ,  G11C5/14 ,  G11C16/32 ,  G11C29/14

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C8/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C29/14 ,  G11C2207/2227

Abstract: The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.

公开(公告)号：US09634019B1

公开(公告)日：2017-04-25

申请号：US15225393

申请日：2016-08-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/66 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/8238 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

公开(公告)号：US20170103989A1

公开(公告)日：2017-04-13

申请号：US15225425

申请日：2016-08-01

Applicant: Silicon Storage Technology, Inc.

Inventor： CHIEN SHENG SU ,  MANDANA TADAYONI ,  NHAN DO

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L21/762 ,  H01L21/84 ,  H01L29/08

CPC classification number: H01L27/11521 ,  H01L21/02532 ,  H01L21/02634 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11531 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are formed in the second area of the substrate.

公开(公告)号：US20170098654A1

公开(公告)日：2017-04-06

申请号：US15225393

申请日：2016-08-01

Applicant: Silicon Storage Technology, Inc.

Inventor： FENG ZHOU ,  XIAN LIU ,  JENG-WEI YANG ,  CHIEN-SHENG SU ,  NHAN DO

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/8238 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

公开(公告)号：US09589630B2

公开(公告)日：2017-03-07

申请号：US14435251

申请日：2013-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Yao Zhou ,  Xiaozhou Qian ,  Guangming Lin

IPC: G11C11/56 ,  G11C7/12 ,  G11C16/28 ,  G05F3/26 ,  G11C5/14

CPC classification number: G11C11/5642 ,  G05F3/262 ,  G11C5/147 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28 ,  G11C2207/063

Abstract: The invention comprises a non-volatile memory device with a sensing amplifier that includes a current mirror comprising a pair of resistors.

Abstract translation: 本发明包括具有感测放大器的非易失性存储器件，该感测放大器包括包括一对电阻器的电流镜。

公开(公告)号：US20160336072A1

公开(公告)日：2016-11-17

申请号：US15084955

申请日：2016-03-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Viktor Markov ,  Jong-Won Yoo ,  Xiao Yan Pi ,  Alexander Kotov

IPC: G11C16/12 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0425 ,  G11C16/10

Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.

Abstract translation: 所公开的实施例包括闪存器件和以与现有技术方法相比降低器件劣化的方式对器件进行编程的方法。

公开(公告)号：US20160240260A1

公开(公告)日：2016-08-18

申请号：US15135346

申请日：2016-04-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

Abstract translation: 非易失性存储器件包括第一导电类型的半导体衬底。 非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。