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829 条记录 (耗时 0.021 秒)

    Light-Emitting Diodes on Concave Texture Substrate
    61.
    发明申请
    Light-Emitting Diodes on Concave Texture Substrate 有权
    凹面纹理基板上的发光二极管

    公开(公告)号：US20120119236A1

    公开(公告)日：2012-05-17

    申请号：US13358327

    申请日：2012-01-25

    申请人： Chen-Hua Yu ,  Hung-Ta Lin ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

    发明人： Chen-Hua Yu ,  Hung-Ta Lin ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

    IPC分类号： H01L27/15 ,  H01L33/48

    CPC分类号： H01L33/48 ,  H01L33/20 ,  H01L33/24

    摘要： A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.

    摘要翻译： 提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。 对衬底进行图案化和蚀刻以形成凹陷。 沿着凹部的底部形成分离层。 沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。 在这些实施例中，与平面表面相比，LED结构的表面积增加。 在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。 在这些实施例中，硅衬底中的凹陷导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

    Wafer bonding
    66.
    发明授权
    Wafer bonding 有权
    晶圆接合

    公开(公告)号：US08119500B2

    公开(公告)日：2012-02-21

    申请号：US11740178

    申请日：2007-04-25

    申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L21/30

    CPC分类号： H01L21/2007

    摘要： A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.

    摘要翻译： 提供了提供堆叠晶片配置的方法。 该方法包括将第一晶片接合到第二晶片。 将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。 填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。 可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。 此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。 在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。

    Flip Chip Substrate Package Assembly and Process for Making Same
    68.
    发明申请
    Flip Chip Substrate Package Assembly and Process for Making Same 审中-公开
    倒装芯片基板封装组装及其制造方法

    公开(公告)号：US20120032337A1

    公开(公告)日：2012-02-09

    申请号：US12852196

    申请日：2010-08-06

    申请人： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

    发明人： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

    IPC分类号： H01L23/498 ,  H01L21/50 ,  H05K1/18

    CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10674

    摘要： Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art.

    摘要翻译： 用于提供用于倒装芯片集成电路的封装衬底和组件的装置和方法。 提供了一种衬底，其具有焊接掩模层，用于导电凸块焊盘的焊料掩模层中的开口，以及在焊料掩模层之间的焊料掩模层中的暴露出阻焊掩模层下面的介电层的开口。 使用热回流将倒装芯片集成电路附接到基板，以将集成电路上的导电焊料凸起回流到导电凸块焊盘。 底部填充材料被分配在集成电路下面并物理接触衬底的电介质层。 在另外的实施例中，将一个或多个集成电路倒装芯片安装到基板。 所得组件相对于现有技术的组件具有改善的热特性。

    Apparatus for storing substrates
    69.
    发明授权
    Apparatus for storing substrates 有权
    用于存储基板的装置

    公开(公告)号：US08109407B2

    公开(公告)日：2012-02-07

    申请号：US11755508

    申请日：2007-05-30

    申请人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Jean Wang ,  Jui-Pin Hung ,  Ming-Shih Yeh

    发明人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Jean Wang ,  Jui-Pin Hung ,  Ming-Shih Yeh

    IPC分类号： B65D45/28 ,  B65D53/06

    CPC分类号： H01L21/67373 ,  H01L21/67376 ,  H01L21/67389

    摘要： An apparatus includes an enclosure and a door configured to seal the enclosure. The door includes a plate. A rotational apparatus is disposed over the plate. At least one first member with a first arm extends from a first rib of the first member. At least one second member with a second arm extends from a second rib of the second member. The first and second arms are connected to the rotational apparatus. At least one corner member has a first edge. The first edge has a shape corresponding to a shape of a corner of the frame. The corner member is connected to a first end of the third arm. A second end of the third arm is connected to the rotational apparatus. A sealing material is disposed along a first longitudinal side of the first rib and a second longitudinal side of the second rib.

    摘要翻译： 一种装置包括外壳和构造成密封外壳的门。 门包括一个板。 旋转装置设置在板上。 具有第一臂的至少一个第一构件从第一构件的第一肋延伸。 具有第二臂的至少一个第二构件从第二构件的第二肋延伸。 第一和第二臂连接到旋转装置。 至少一个角部件具有第一边缘。 第一边缘具有与框架的角部的形状对应的形状。 角部件连接到第三臂的第一端。 第三臂的第二端连接到旋转装置。 密封材料沿着第一肋的第一纵向侧面和第二肋的第二纵向侧面设置。

    FinFETs having dielectric punch-through stoppers
    70.
    发明授权
    FinFETs having dielectric punch-through stoppers 有权
    FinFET具有绝缘穿孔塞

    公开(公告)号：US08106459B2

    公开(公告)日：2012-01-31

    申请号：US12116074

    申请日：2008-05-06

    申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

    发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

    IPC分类号： H01L21/00

    CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7851

    摘要： A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

    摘要翻译： 半导体结构包括半导体衬底; 在所述半导体衬底的第一部分上的平面晶体管，其中所述半导体衬底的所述第一部分具有第一顶表面; 以及在半导体衬底的第二部分上的多栅极晶体管。 半导体衬底的第二部分从第一顶表面凹入以形成多栅晶体管的鳍。 翅片通过绝缘体与半导体衬底电隔离。