公开(公告)号：US20120068218A1

公开(公告)日：2012-03-22

申请号：US12884570

申请日：2010-09-17

申请人： Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Ping Hung ,  Chien Ling Hwang ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Ping Hung ,  Chien Ling Hwang ,  Chen-Hua Yu

IPC分类号： H01L33/62 ,  H01L21/50

CPC分类号： H01L33/642 ,  H01L33/486 ,  H01L33/647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2933/0033 ,  H01L2933/0075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire.

摘要翻译： 本公开提供了一种用于光子器件（例如发光二极管器件）的封装方法。 包装包括绝缘结构。 该包装包括各自延伸穿过绝缘结构的第一和第二导电结构。 发光二极管器件的底面的实质区域与第一导电结构的顶表面直接接触。 发光二极管器件的顶表面通过接合线接合到第二导电结构。

公开(公告)号：US08946742B2

公开(公告)日：2015-02-03

申请号：US12897124

申请日：2010-10-04

申请人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

发明人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC分类号： H01L33/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L33/48 ,  H01L33/64 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

摘要翻译： 具有上述通孔硅衬底（或通孔）的基板消除了对导电凸块的需要。 流程非常简单，成本效益高。 所描述的结构将单独的TSV，再分配层和导电凸块结构组合成单个结构。 通过组合单独的结构，产生具有高散热能力的低电阻电连接。 此外，具有通过硅插头（或通孔或沟槽）的基板还允许将多个芯片封装在一起。 通过硅沟槽可围绕一个或多个芯片，以在制造期间提供防止铜扩散到相邻器件的保护。 此外，具有相似或不同功能的多个芯片可以集成在TSV基板上。 通过具有不同图案的硅插头可以在半导体芯片下使用以改善散热并解决制造问题。

公开(公告)号：US08507940B2

公开(公告)日：2013-08-13

申请号：US12879584

申请日：2010-09-10

申请人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

发明人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC分类号： H01L33/00

CPC分类号： H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

摘要翻译： 具有上述通孔硅封装（或通孔）的封装衬底为需要热管理的半导体芯片提供侧向和垂直散热​​路径。 具有高占空比的通过硅插头（TSP）的设计可以最有效地提供散热。 具有双面梳状图案的TSP设计可以提供等于或大于50％的高占空比。 具有高占空比的封装衬底对于产生大量热量的半导体芯片是有用的。 这种半导体芯片的例子是发光二极管（LED）芯片。

公开(公告)号：US08580682B2

公开(公告)日：2013-11-12

申请号：US12895296

申请日：2010-09-30

申请人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.

摘要翻译： 一种器件包括具有第一表面的衬底和与第一表面相对的第二表面。 贯穿基板通孔（TSV）从基板的第一表面延伸到第二表面。 电介质层设置在衬底上。 金属焊盘设置在电介质层中并物理接触TSV，其中金属焊盘和TSV由相同的材料形成，并且其中由不同于相同材料的材料形成的层不在其间并且使TSV和 金属垫彼此分开。

公开(公告)号：US20120083116A1

公开(公告)日：2012-04-05

申请号：US12895296

申请日：2010-09-30

申请人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.

摘要翻译： 一种器件包括具有第一表面的衬底和与第一表面相对的第二表面。 贯穿基板通孔（TSV）从基板的第一表面延伸到第二表面。 电介质层设置在衬底上。 金属焊盘设置在电介质层中并物理接触TSV，其中金属焊盘和TSV由相同的材料形成，并且其中由不同于相同材料的材料形成的层不在其间并且使TSV和 金属垫彼此分开。

公开(公告)号：US20110193221A1

公开(公告)日：2011-08-11

申请号：US12774558

申请日：2010-05-05

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L21/50 ,  H01L23/488

CPC分类号： H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00012

摘要： A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

摘要翻译： 一种装置包括插入件，其包括具有顶表面的基板。 互连结构形成在衬底的顶表面上，其中互连结构包括至少一个电介质层，以及至少一个电介质层中的金属特征。 多个穿通基板通孔（TSV）在基板中并电耦合到互连结构。 第一个模具结束并粘贴到插入器上。 第二管芯被结合到插入件上，其中第二管芯在互连结构之下。

公开(公告)号：US08866301B2

公开(公告)日：2014-10-21

申请号：US12781960

申请日：2010-05-18

申请人： Yung-Chi Lin ,  Jing-Cheng Lin ,  Chen-Hua Yu

发明人： Yung-Chi Lin ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/29 ,  H01L21/48

CPC分类号： H01L21/4857 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

摘要翻译： 封装系统包括设置在插入器上的第一集成电路。 所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。 第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。 第一集成电路与第一互连结构电耦合。

公开(公告)号：US10297550B2

公开(公告)日：2019-05-21

申请号：US12774558

申请日：2010-05-05

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC分类号： H01L23/538 ,  H01L23/488 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US08803316B2

公开(公告)日：2014-08-12

申请号：US13311692

申请日：2011-12-06

申请人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

发明人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

摘要翻译： 一种器件包括具有正面和背面的衬底，从衬底的背面延伸到前侧的通孔，以及位于衬底的背面和通孔上方的导电焊盘。 导电垫具有基本平坦的顶表面。 导电凸块在基本上平坦的顶表面上方具有非平面的顶表面，并且与通孔对准。 导电凸块和导电垫由相同的材料形成。 在导电凸块和导电垫之间不形成界面。

公开(公告)号：US08405201B2

公开(公告)日：2013-03-26

申请号：US12836720

申请日：2010-07-15

申请人： Yung-Chi Lin ,  Weng-Jin Wu ,  Shau-Lin Shue

发明人： Yung-Chi Lin ,  Weng-Jin Wu ,  Shau-Lin Shue

IPC分类号： H01L23/48

CPC分类号： H01L21/76871 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof.

摘要翻译： 半导体衬底具有前表面和后表面，并且形成TSV结构以延伸穿过半导体衬底。 TSV结构包括金属层，围绕金属层的金属籽晶层，围绕金属种子层的阻挡层，以及形成在夹在金属层和金属籽晶层之间的部分中的阻挡层。 阻挡层包括镁（Mg），铁（Fe），钴（Co），镍（Ni），钛（Ti），铬（Cr），钽（Ta），钨（W），镉（Cd） 其组合。