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公开(公告)号：US20160181073A1
公开(公告)日：2016-06-23
申请号：US15055243
申请日：2016-02-26
发明人： Ping-Yin Liu , Xin-Hua Huang , Lee-Chuan Tseng , Lan-Lin Chao
CPC分类号： H01J37/32834 , C23C16/45565 , C23C16/50 , C23C16/52 , H01J37/3244 , H01J37/32449 , H01J37/32568 , H01J37/32853 , H01J37/32862 , H01J37/32917 , H01J37/32972 , H01L21/3065 , H01L21/67017
摘要： An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.
摘要翻译： 一个实施方案的低污染室包括气体入口，可调顶部电极和可调底部电极。 低污染室被配置为响应于期望的等离子体密度和在表面激活过程期间在可调顶部电极和可调底部电极之间测量的等离子体的测量密度来调节可调节顶部电极和可调节底部电极之间的距离 。 低污染室还包括出口。
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公开(公告)号：US20160163684A1
公开(公告)日：2016-06-09
申请号：US15042268
申请日：2016-02-12
发明人： Bruce C.S. Chou , Chen-Jong Wang , Ping-Yin Liu , Jung-Kuo Tu , Tsung-Te Chou , Xin-Hua Huang , Hsun-Chung Kuang , Lan-Lin Chao , Chia-Shiung Tsai , Xiaomeng Chen
IPC分类号： H01L25/00 , H01L21/308 , H01L23/00 , H01L21/764
CPC分类号： H01L24/80 , H01L21/3081 , H01L21/764 , H01L23/498 , H01L23/5226 , H01L23/53204 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/83 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/03845 , H01L2224/05554 , H01L2224/05571 , H01L2224/05647 , H01L2224/0601 , H01L2224/08147 , H01L2224/0901 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2924/00011 , H01L2924/01322 , H01L2924/351 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/81805
摘要： A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
摘要翻译： 封装部件包括表面电介质层，其包括平面顶表面，表面电介质层中的金属焊盘，并且包括具有平坦顶表面的第二平面顶表面水平面和在金属焊盘一侧的空气沟槽。 金属垫的侧壁暴露于空气沟槽。
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公开(公告)号：US20160155665A1
公开(公告)日：2016-06-02
申请号：US15018422
申请日：2016-02-08
发明人： Hsun-Chung Kuang , Yen-Chang Chu , Cheng-Tai Hsiao , Ping-Yin Liu , Lan-Lin Chao , Yeur-Luen Tu , Chia-Shiung Tsai , Xiaomeng Chen
IPC分类号： H01L21/768 , H01L25/00
CPC分类号： H01L21/76883 , H01L21/76805 , H01L23/291 , H01L23/293 , H01L23/3192 , H01L23/538 , H01L23/5385 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/10 , H01L24/18 , H01L24/80 , H01L24/89 , H01L25/043 , H01L25/0657 , H01L25/0756 , H01L25/50 , H01L2224/03616 , H01L2224/05124 , H01L2224/05147 , H01L2224/05547 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/80097 , H01L2224/80201 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2225/06513 , H01L2924/01029 , H01L2924/01322 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
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公开(公告)号：US20150287694A1
公开(公告)日：2015-10-08
申请号：US14725266
申请日：2015-05-29
发明人： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L23/00
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/74 , H01L24/94 , H01L2224/02215 , H01L2224/0361 , H01L2224/03616 , H01L2224/0381 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/7565 , H01L2224/75753 , H01L2224/75824 , H01L2224/80004 , H01L2224/80007 , H01L2224/8001 , H01L2224/80011 , H01L2224/80013 , H01L2224/80014 , H01L2224/80065 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80136 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83889 , H01L2224/94 , H01L2924/00014 , H01L2924/1461 , H01L2924/351 , Y10T156/15 , Y10T156/1744 , H01L2924/00012 , H01L2224/80 , H01L2924/05442 , H01L2924/00
摘要： Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
摘要翻译： 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。
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公开(公告)号：US09142517B2
公开(公告)日：2015-09-22
申请号：US13664796
申请日：2012-10-31
发明人： Ping-Yin Liu , Szu-Ying Chen , Chen-Jong Wang , Chih-Hui Huang , Xin-Hua Huang , Lan-Lin Chao , Yeur-Luen Tu , Chia-Chiung Tsai , Xiaomeng Chen
IPC分类号： H01L23/00 , H01L23/532 , H01L21/768 , H01L25/00 , H01L25/065
CPC分类号： H01L24/03 , H01L21/76831 , H01L21/76834 , H01L23/53238 , H01L23/53295 , H01L24/05 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/0348 , H01L2224/0361 , H01L2224/03616 , H01L2224/05026 , H01L2224/0508 , H01L2224/05147 , H01L2224/05187 , H01L2224/05547 , H01L2224/05553 , H01L2224/05564 , H01L2224/05571 , H01L2224/05576 , H01L2224/05578 , H01L2224/05647 , H01L2224/05687 , H01L2224/08121 , H01L2224/08147 , H01L2224/80121 , H01L2224/80203 , H01L2225/06513 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05032 , H01L2924/0504 , H01L2924/05442 , H01L2924/00012 , H01L2924/05042 , H01L2924/059 , H01L2224/05552
摘要： The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers.
摘要翻译： 上述扩散阻挡层的实施例提供了用于形成铜扩散阻挡层以防止晶片的混合结合的器件劣化的机制。 扩散阻挡层围绕用于混合键合的含铜导电焊盘。 扩散阻挡层可以在两个接合晶片中的一个上或两个接合晶片上。
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公开(公告)号：US09099476B2
公开(公告)日：2015-08-04
申请号：US14073714
申请日：2013-11-06
发明人： Yuan-Chih Hsieh , Li-Cheng Chu , Ming-Tung Wu , Ping-Yin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
摘要翻译： 本公开提供了通孔结构及其制造方法的各种实施例。 在一个示例中，通孔结构包括具有由半导体衬底限定的通孔侧壁表面的通孔。 通孔侧壁表面具有第一部分和第二部分。 在通路侧壁表面的第一部分上的通路中设置导电层，并且介电层设置在通孔侧壁表面的第二部分上。 电介质层设置在通孔侧壁表面的第二部分和导电层之间。 在一个实例中，电介质层是氧化物层。
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公开(公告)号：US20150064810A1
公开(公告)日：2015-03-05
申请号：US14015556
申请日：2013-08-30
发明人： Ping-Yin Liu , Xin-Hua Huang , Lee-Chuan Tseng , Lan-Lin Chao
IPC分类号： H01L21/66 , H01L21/67 , H01J37/32 , H01L21/3065
CPC分类号： H01J37/32834 , C23C16/45565 , C23C16/50 , C23C16/52 , H01J37/3244 , H01J37/32449 , H01J37/32568 , H01J37/32853 , H01J37/32862 , H01J37/32917 , H01J37/32972 , H01L21/3065 , H01L21/67017
摘要： An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, an adjustable bottom electrode, and an outlet. The chamber is configured to adjust a distance between the adjustable top and bottom electrodes in accordance with a desired density of plasma disposed between the top electrode and the bottom electrode.
摘要翻译： 一个实施方案的低污染室包括气体入口，可调顶部电极，可调底部电极和出口。 腔室被配置为根据设置在顶部电极和底部电极之间的等离子体的期望密度来调整可调节顶部和底部电极之间的距离。
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公开(公告)号：US11508562B2
公开(公告)日：2022-11-22
申请号：US15055243
申请日：2016-02-26
发明人： Ping-Yin Liu , Xin-Hua Huang , Lee-Chuan Tseng , Lan-Lin Chao
IPC分类号： H01J37/32 , H01L21/67 , H01L21/3065 , C23C16/50 , C23C16/52 , C23C16/455
摘要： An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.
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公开(公告)号：US11014805B2
公开(公告)日：2021-05-25
申请号：US16544234
申请日：2019-08-19
发明人： Chun-wen Cheng , Hung-Chia Tsai , Lan-Lin Chao , Yuan-Chih Hsieh , Ping-Yin Liu
IPC分类号： B81C1/00
摘要： A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
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公开(公告)号：US10790189B2
公开(公告)日：2020-09-29
申请号：US16149972
申请日：2018-10-02
发明人： Hsun-Chung Kuang , Yen-Chang Chu , Cheng-Tai Hsiao , Ping-Yin Liu , Lan-Lin Chao , Yeur-Luen Tu , Chia-Shiung Tsai , Xiaomeng Chen
IPC分类号： H01L25/04 , H01L23/538 , H01L25/065 , H01L21/768 , H01L23/00 , H01L23/31 , H01L25/075 , H01L23/29 , H01L25/00
摘要： An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
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