公开(公告)号：US20140104799A1

公开(公告)日：2014-04-17

申请号：US13783161

申请日：2013-03-01

申请人： UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD. ,  UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD.

发明人： JENCHUN CHEN ,  HSIN CHIN CHANG

IPC分类号： H05K1/02

CPC分类号： H05K1/0284 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/144 ,  H05K3/284 ,  H05K2201/042 ,  H05K2201/2018 ,  H05K2203/1316 ,  H01L2924/00012

摘要： A 3D stacked package structure includes a first unit, a molding unit, a conductive unit and a second unit. The first unit includes a first substrate and at least one first electronic component, and the first substrate has at least one runner and at least one first conductive pad. The molding unit includes a top portion, a frame, and at least one connection connected between the top portion and the frame. The conductive unit includes at least one conductor passing through the frame and electrically connected to the first conductive pad. Therefore, the first unit can be stacked on the second unit through the frame of the molding unit, and the first unit can be electrically connected to the second unit through the conductor of the conductive unit.

摘要翻译： 3D堆叠封装结构包括第一单元，模制单元，导电单元和第二单元。 第一单元包括第一基板和至少一个第一电子部件，并且第一基板具有至少一个流道和至少一个第一导电垫。 模制单元包括顶部，框架和连接在顶部和框架之间的至少一个连接。 导电单元包括至少一个穿过框架并且电连接到第一导电垫的导体。 因此，第一单元可以通过模制单元的框架堆叠在第二单元上，并且第一单元可以通过导电单元的导体与第二单元电连接。

公开(公告)号：US20140061899A1

公开(公告)日：2014-03-06

申请号：US13846608

申请日：2013-03-18

申请人： CHIPMOS TECHNOLOGIES INC

发明人： TSUNG JEN LIAO

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73277 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

摘要翻译： 本发明提供一种半导体封装结构，其包括管芯，多个接合线，密封剂和多个第一外部端子。 模具具有活性表面和背面。 每个接合线的第一端连接到管芯的后表面，并且与第一端相对的第二端电连接到管芯的有效表面。 密封剂覆盖管芯的背面和接合线，其中每个接合线的一部分从密封剂露出。 第一外部端子设置在密封剂的顶表面上，并且分别覆盖接合线的暴露部分并且电连接到接合线。

公开(公告)号：US20140008795A1

公开(公告)日：2014-01-09

申请号：US13922722

申请日：2013-06-20

申请人： Jongkook KIM ,  Su-min PARK ,  Soojeoung PARK ,  Bona BAEK ,  Hohyeuk IM ,  Byoungwook JANG ,  Yoonha JUNG

发明人： Jongkook KIM ,  Su-min PARK ,  Soojeoung PARK ,  Bona BAEK ,  Hohyeuk IM ,  Byoungwook JANG ,  Yoonha JUNG

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.

摘要翻译： 提供半导体封装及其制造方法。 封装基板包括孔，其可用于形成没有任何空隙的模具层。 可以部分去除模具层以暴露下部导电图案。 因此，可以提高焊球的布线性。

公开(公告)号：US20130277801A1

公开(公告)日：2013-10-24

申请号：US13790097

申请日：2013-03-08

申请人： MEDIATEK INC.

发明人： Nan-Cheng CHEN ,  Tung-Hsien HSIEH

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L25/105 ,  H01L27/0248 ,  H01L27/1255 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a lower chip package; an upper chip package disposed on an upper surface of the lower chip package; at least one conducting element disposed between the lower chip package and the upper chip package; and at least one decoupling capacitor disposed on the upper surface of the lower chip package, wherein the decoupling capacitor is not covered by the upper chip package, and the decoupling capacitor is electrically connected to a power line or a ground line in the lower chip package.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：一个较低的芯片封装; 上芯片封装，设置在下芯片封装的上表面上; 设置在下芯片封装和上芯片封装之间的至少一个导电元件; 以及设置在下芯片封装的上表面上的至少一个去耦电容器，其中去耦电容器不被上芯片封装覆盖，并且去耦电容器电连接到下芯片封装中的电源线或接地线 。

公开(公告)号：US08557629B1

公开(公告)日：2013-10-15

申请号：US12959911

申请日：2010-12-03

申请人： Jin Seong Kim ,  Dong Joo Park ,  Kwang Ho Kim ,  Hee Yeoul Yoo ,  Jeong Wung Jeong

发明人： Jin Seong Kim ,  Dong Joo Park ,  Kwang Ho Kim ,  Hee Yeoul Yoo ,  Jeong Wung Jeong

IPC分类号： H01L21/00 ,  H01L31/0232 ,  H01L23/28

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/18301

摘要： Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.

公开(公告)号：US20130200513A1

公开(公告)日：2013-08-08

申请号：US13536905

申请日：2012-06-28

申请人： Jiun Yi WU

发明人： Jiun Yi WU

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/172 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： Mechanisms of forming a package on package (PoP) package by using an interposer and an no-reflow underfill (NUF) layer are provided. The interposer frame improves the form factor of the package, enables the reduction in the pitch of the bonding structures. The NUF layer enables a semiconductor die and an interposer frame be bonded to a substrate by utilizing the heat on the connectors of the semiconductor die and on the connectors of the interposer frame for bonding. The heat provided by the semiconductor die and the interposer frame also transforms the NUF layer into an underfill. PoP structures formed by using the interposer frame and the NUF layer improve yield and have better reliability performance.

摘要翻译： 提供了通过使用插入器和无回流底部填充（NUF）层在封装（PoP）封装上形成封装的机制。 插入器框架改善了封装的外形尺寸，能够降低接合结构的间距。 通过利用半导体管芯的连接器上的热量和用于接合的插入器框架的连接器，NUF层能够使半导体管芯和插入器框架结合到衬底。 由半导体管芯和内插器框架提供的热量也将NUF层转变成底部填充物。 通过使用插入框架和NUF层形成的PoP结构提高了产量并具有更好的可靠性性能。

公开(公告)号：US20130099387A1

公开(公告)日：2013-04-25

申请号：US13277330

申请日：2011-10-20

申请人： Terrence Caskey ,  Ilyas Mohammed

发明人： Terrence Caskey ,  Ilyas Mohammed

IPC分类号： H01L23/522 ,  H01L21/66

CPC分类号： H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/852 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

摘要： A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

摘要翻译： 微电子封装可以包括第一微电子单元，其包括具有第一芯片触点的半导体芯片，与半导体芯片的边缘接触的密封剂以及暴露在密封剂的表面处并与第一芯片触点电连接的第一单元触点。 封装可以包括第二微电子单元，其包括在其表面具有第二芯片触点的半导体芯片，以及与第二单元的芯片的边缘接触并且具有远离边缘延伸的表面的密封剂。 芯片的表面和第二单元的密封剂的表面限定了第二单元的面。 表面处的封装端子可以通过与第一单元触点电连接的接合线与第一单元触点电连接，并且第二芯片通过金属化通孔和与第二芯片触点接触形成的迹线接触。

公开(公告)号：US20130001767A1

公开(公告)日：2013-01-03

申请号：US13534409

申请日：2012-06-27

申请人： Atsunori KAJIKI

发明人： Atsunori KAJIKI

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/49811 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00

摘要： A method for manufacturing a package, includes preparing a substrate having a first surface on which a connecting pad is formed, mounting a sacrificing material on the connecting pad, forming a package portion covering the first surface of the substrate, exposing the sacrificing material from a surface of the package portion, and removing the exposed sacrificing material from the side of the surface of the package portion, and forming an opening portion in the package portion on the connecting pad.

摘要翻译： 一种制造封装的方法，包括制备具有第一表面的基板，在其上形成连接焊盘，将牺牲材料安装在连接焊盘上，形成覆盖基板的第一表面的封装部分，将牺牲材料从 并且从封装部分的表面侧去除暴露的牺牲材料，并且在连接焊盘上的封装部分中形成开口部分。

公开(公告)号：US07808094B2

公开(公告)日：2010-10-05

申请号：US12022234

申请日：2008-01-30

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Koichi Nagai ,  Naoki Suzuki

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Koichi Nagai ,  Naoki Suzuki

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2224/0401 ,  H01L2924/00

摘要： A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips. At least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are opposed to each other, at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, and all or a part of the one semiconductor chip is arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member.

摘要翻译： 半导体芯片的堆叠结构包括多个堆叠半导体芯片和保持各个半导体芯片的多个平板状保持构件。 保持构件中的至少两个保持构件布置在保持构件的内侧面彼此相对的半导体芯片的端部的位置处，由两个保持构件保持的两个半导体芯片中的至少一个半导体芯片， 分别由半导体芯片的一端的保持构件的一个保持构件保持，并且一个半导体芯片的全部或一部分配置在位于另一个的内侧面的内侧的最大空间 保持构件的保持构件，由包括另一个保持构件的一个表面的表面形成的最大空间，包括另一个保持构件的另一个表面的表面以及包括由另一个保持构件的另一个表面保持的另一个半导体芯片的表面的表面 另一个保持构件，另一个半导体芯片更靠近另一个保持构件。

公开(公告)号：US20080116559A1

公开(公告)日：2008-05-22

申请号：US11979785

申请日：2007-11-08

申请人： Masayuki Hosono ,  Akiji Shibata ,  Kimio Inaba

发明人： Masayuki Hosono ,  Akiji Shibata ,  Kimio Inaba

IPC分类号： H01L23/488

CPC分类号： H01L25/105 ,  H01L23/4985 ,  H01L24/50 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48

摘要： A semiconductor device has a semiconductor element; an interposer substrate having a wiring pattern electrically connected to the semiconductor element and an insulating substrate formed with the wiring pattern; a connection layer for adhering between the semiconductor element and the interposer substrate; and a solder ball external terminal arranged on the interposer substrate. The insulating substrate is folded in a portion mounted with the external terminal arranged on an outer side to the semiconductor element, and the unfolded and folded portions of the insulating substrate are opposite each other to form a gap therebetween.

摘要翻译： 半导体器件具有半导体元件; 具有与半导体元件电连接的布线图案的内插基板和形成有布线图案的绝缘基板; 用于粘附在所述半导体元件和所述插入器基板之间的连接层; 以及布置在插入器基板上的焊球外部端子。 绝缘基板被折叠在安装有外部端子的部分上，该外部端子布置在半导体元件的外侧，并且绝缘基板的展开和折叠部分彼此相对以在它们之间形成间隙。