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    Schemes for Forming Barrier Layers for Copper in Interconnect Structures
    74.
    发明申请
    Schemes for Forming Barrier Layers for Copper in Interconnect Structures 有权
    在互连结构中形成铜屏障层的方案

    公开(公告)号：US20110223762A1

    公开(公告)日：2011-09-15

    申请号：US13115161

    申请日：2011-05-25

    申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    IPC分类号： H01L21/283

    CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

    摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

    Schemes for forming barrier layers for copper in interconnect structures
    75.
    发明授权
    Schemes for forming barrier layers for copper in interconnect structures 有权
    用于在互连结构中形成铜的阻挡层的方案

    公开(公告)号：US07964496B2

    公开(公告)日：2011-06-21

    申请号：US11602808

    申请日：2006-11-21

    申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

    摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

    CxHy sacrificial layer for cu/low-k interconnects
    78.
    发明授权
    CxHy sacrificial layer for cu/low-k interconnects 有权
    CxHy用于cu / low-k互连的牺牲层

    公开(公告)号：US07365026B2

    公开(公告)日：2008-04-29

    申请号：US11048215

    申请日：2005-02-01

    申请人： Shwang-Ming Jeng ,  Ming Ling Yeh ,  Tien-I Bao ,  Keng-Chu Lin

    发明人： Shwang-Ming Jeng ,  Ming Ling Yeh ,  Tien-I Bao ,  Keng-Chu Lin

    IPC分类号： H01L21/469 ,  H01L23/58

    CPC分类号： H01L21/02274 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/312 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831

    摘要： A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.

    摘要翻译： 提供涉及低k电介质的半导体制造方法。 该方法包括在低k电介质的表面上沉积一般组合物C x H y Y y的烃。 烃层通过使前体材料，优选C 2 H 4 H 3或（CH 3）3 H 2， CHC 6 6 H 3 CH 3，使用PECVD法。 根据本发明的实施例，碳扩散到低k电介质中，由此降低由等离子体处理或蚀刻引起的低k电介质损伤。 其他实施例包括具有低k电介质的半导体器件，其中低k电介质具有邻近沟槽侧壁和大块电介质区域的碳调节介电区域。 在优选的实施方案中，碳调节的电介质区域的碳浓度比体电介质区域的碳浓度小约不超过约5％。

    Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity
    79.
    发明授权
    Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity 有权
    形成假铜塞以改善低k结构机械强度和塞填充均匀性的方法

    公开(公告)号：US06887790B1

    公开(公告)日：2005-05-03

    申请号：US10199856

    申请日：2002-07-19

    申请人： Tien-I Bao ,  Bi-Trong Chen ,  Ying-Ho Chen

    发明人： Tien-I Bao ,  Bi-Trong Chen ,  Ying-Ho Chen

    IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76838 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A new method is provided for the creation of dummy plugs in support of creating a robust structure of overlying interconnect traces. A pattern of holes for dummy plugs is etched stopping at an etch stop layer, the etch stop layer is then removed from the bottom of the holes that have been created whereby this removal is extended into an underlying layer of insulating material. The pattern of holes is filled with a metal, preferably copper, excess metal is removed by methods of Chemical Mechanical Polishing, leaving in place a pattern of metal plugs that penetrate through layers of insulation material and through layers of etch stop material and into an underlying layer of semiconductor material.

    摘要翻译： 提供了一种新的方法来创建虚拟插头，以支持创建上层互连线路的稳健结构。 在蚀刻停止层处蚀刻停止用于虚拟插头的孔的图案，然后从已经形成的孔的底部去除蚀刻停止层，由此将该去除延伸到下面的绝缘材料层中。 孔的图案填充有金属，优选铜，通过化学机械抛光的方法除去多余的金属，留下穿过绝缘材料层并通过蚀刻停止材料层的金属塞的图案，并进入下面的 半导体材料层。

    Minimizing coating defects in low dielectric constant films
    80.
    发明授权
    Minimizing coating defects in low dielectric constant films 有权
    最小化低介电常数膜中的涂层缺陷

    公开(公告)号：US06667249B1

    公开(公告)日：2003-12-23

    申请号：US10101655

    申请日：2002-03-20

    申请人： Yu-Hui Chen ,  Tien-I Bao ,  Yao-Yi Cheng

    发明人： Yu-Hui Chen ,  Tien-I Bao ,  Yao-Yi Cheng

    IPC分类号： H01L2131

    CPC分类号： H01L21/02118 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76829

    摘要： A method of coating a low dielectric constant material layer wherein the wafer surface is pre-wetted using a solvent to prevent or reduce coating defects is described. A semiconductor substrate is provided wherein a top surface of the semiconductor substrate may have surface defects. A solvent is coated overlying the top surface of the semiconductor substrate. A low dielectric constant material layer is coated overlying the solvent wherein the solvent covers the surface defects thereby preventing defects in the low dielectric constant material layer.

    摘要翻译： 描述了一种涂覆低介电常数材料层的方法，其中晶片表面使用溶剂预先润湿以防止或减少涂层缺陷。 提供半导体衬底，其中半导体衬底的顶表面可能具有表面缺陷。 将溶剂涂覆在半导体衬底的顶表面上。 将低介电常数材料层涂覆在溶剂上，其中溶剂覆盖表面缺陷从而防止低介电常数材料层中的缺陷。