公开(公告)号：US20160379040A1

公开(公告)日：2016-12-29

申请号：US15177143

申请日：2016-06-08

申请人： XINTEC INC.

发明人： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： G06K9/00 ,  G06F3/041

CPC分类号： G06K9/00013 ,  G06F3/041 ,  G06F2203/04103

摘要： This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.

摘要翻译： 本发明提供了一种触摸面板感测芯片封装模块复合体，包括：具有第一顶表面和彼此相对的第一底表面的触摸面板，其中所述第一底表面具有第一腔体，所述第一腔体具有被侧壁包围的底壁 ; 形成在所述底壁和与所述空腔相邻的所述第一底面的着色层; 以及通过形成在腔的底壁上的着色层与腔体结合的芯片尺度感测芯片封装模块。

公开(公告)号：US20160218140A1

公开(公告)日：2016-07-28

申请号：US15086809

申请日：2016-03-31

申请人： XINTEC INC.

发明人： Wei-Ming CHIEN ,  Chia-Sheng LIN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L27/146

CPC分类号： H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

摘要： A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

摘要翻译： 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

公开(公告)号：US20160218129A1

公开(公告)日：2016-07-28

申请号：US15005956

申请日：2016-01-25

申请人： XINTEC INC.

发明人： Tsang-Yu LIU ,  Chi-Chang LIAO

IPC分类号： H01L27/146

CPC分类号： H01L27/14618 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/13

摘要： A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the first surface and covers the conducting pad. The method also includes bonding the sensing device to a circuit board. The cover plate is removed after bonding the sensing device to the circuit board. The method further includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.

摘要翻译： 提供一种形成光敏模块的方法。 该方法包括提供感测装置。 感测装置包括具有第一表面和与其相对的第二表面的基底。 导电垫位于第一表面上。 第一开口穿透衬底并暴露导电垫。 再分布层位于第一开口中，以电连接到导电垫。 盖板位于第一表面上并覆盖导电垫。 该方法还包括将感测装置接合到电路板。 在将感测装置接合到电路板之后，盖板被去除。 该方法还包括将对应于感测装置的光学部件安装在电路板上。 还提供了通过该方法形成的感光模块。

公开(公告)号：US20160190353A1

公开(公告)日：2016-06-30

申请号：US14860388

申请日：2015-09-21

申请人： XINTEC INC.

发明人： Chi-Chang LIAO ,  Po-Chang HUANG ,  Tsang-Yu LIU

IPC分类号： H01L31/02 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： H01L27/1469 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/16225

摘要： A method for forming a photosensitive module is provided. The method includes providing a substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A cover plate is provided on the first surface of the substrate. An opening is formed. The opening penetrates the substrate and exposes the conducting pad. A redistribution layer is formed in the first opening to electrically connect to the conducting pad. The cover plate is removed and a dicing process is performed to form a sensing device. The sensing device is bonded to a circuit board. An optical component is mounted on the circuit board and corresponds to the sensing device. A photosensitive module formed by the method is also provided.

摘要翻译： 提供一种形成光敏模块的方法。 该方法包括提供具有第一表面和与其相对的第二表面的基底。 导电垫位于第一表面上。 盖板设置在基板的第一表面上。 形成一个开口。 开口穿透衬底并暴露导电垫。 在第一开口中形成再分配层以电连接到导电垫。 去除盖板并执行切割处理以形成感测装置。 感测装置结合到电路板上。 光学部件安装在电路板上并对应于感测装置。 还提供了通过该方法形成的感光模块。

公开(公告)号：US20160181212A1

公开(公告)日：2016-06-23

申请号：US14958672

申请日：2015-12-03

申请人： XINTEC INC.

发明人： Tsang-Yu LIU ,  Po-Han LEE ,  Wei-Ming CHIEN

IPC分类号： H01L23/00 ,  H01L21/78

CPC分类号： H01L24/02 ,  B81C3/00 ,  H01L23/3114 ,  H01L23/315 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/12041 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/81

摘要： A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the first surface of the substrate and includes a conducting pad structure. A first opening penetrates the substrate and exposes a surface of the conducting pad structure. A second opening is communication with the first opening and penetrates the conducting pad structure. A redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the conducting pad structure and is filled into the second opening. A method for forming the chip package is also provided.

摘要翻译： 提供芯片封装。 芯片封装包括具有第一表面和与其相对的第二表面的基板。 电介质层设置在衬底的第一表面上并且包括导电焊盘结构。 第一开口穿透衬底并暴露导电垫结构的表面。 第二开口与第一开口连通并穿透导电垫结构。 再分配层保形地设置在第一开口的侧壁和导电垫结构的表面上，并被填充到第二开口中。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20150179831A1

公开(公告)日：2015-06-25

申请号：US14640307

申请日：2015-03-06

申请人： XINTEC INC.

发明人： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L31/0232 ,  H01L31/028 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/18

CPC分类号： H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

摘要： A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

摘要翻译： 半导体结构包括硅衬底，保护层，电焊盘，隔离层，再分配层，导电层，钝化层和导电结构。 硅基板具有凹形区域，台阶结构，齿结构，第一表面和与第一表面相对的第二表面。 台阶结构和齿结构围绕凹区域。 台阶结构具有第一倾斜表面，第三表面和面对凹入区域并且依次连接的第二倾斜表面。 保护层位于硅衬底的第一表面上。 电焊盘位于保护层中，并通过凹面露出。 隔离层位于第一和第二倾斜表面，台阶结构的第二和第三表面以及齿结构上。

公开(公告)号：US20150097299A1

公开(公告)日：2015-04-09

申请号：US14504319

申请日：2014-10-01

申请人： XINTEC INC.

发明人： Chien-Hui CHEN ,  Tsang-Yu LIU ,  Chun-Wei CHANG ,  Chia-Ming CHENG

IPC分类号： H01L25/065 ,  H01L21/50

CPC分类号： H01L25/0655 ,  H01L21/6835 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

摘要翻译： 提供一种形成芯片封装的方法。 提供第一基板。 第二衬底附接在第一衬底上，其中第二衬底具有由划线区域分隔的多个矩形芯片区域。 去除对应于划线区域的第二基板的一部分，以在第一基板上形成多个芯片，其中在相邻芯片之间形成至少一个桥接部分。 还提供了通过该方法形成的芯片封装。

公开(公告)号：US20150054002A1

公开(公告)日：2015-02-26

申请号：US14464570

申请日：2014-08-20

申请人： XINTEC INC.

发明人： Wei-Ming CHIEN ,  Chia-Sheng LIN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/522 ,  H01L33/62 ,  H01L31/16

CPC分类号： H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

摘要： A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

摘要翻译： 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

公开(公告)号：US20140332983A1

公开(公告)日：2014-11-13

申请号：US14339341

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

摘要翻译： 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US20140332908A1

公开(公告)日：2014-11-13

申请号：US14339360

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN ,  Ho-Yin YIU

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

摘要翻译： 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。