公开(公告)号：US08035198B2

公开(公告)日：2011-10-11

申请号：US12188229

申请日：2008-08-08

Applicant: Hanyi Ding ,  Alvin Jose Joseph ,  Anthony Kendall Stamper

Inventor： Hanyi Ding ,  Alvin Jose Joseph ,  Anthony Kendall Stamper

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/481 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/0405 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01068 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.

Abstract translation: 通过晶片通孔结构。 该结构包括：具有顶表面和相对底表面的半导体衬底; 以及贯穿晶片通孔的阵列，其包括至少一个导电的通过晶片通孔和至少一个非导电的通过晶片通孔，每个通过晶片通孔的通过晶片通孔的阵列从基板的顶表面延伸到更大的 比一半到一路到底层的底面。 也是用于制造晶片通孔结构的方法。

公开(公告)号：US20080230891A1

公开(公告)日：2008-09-25

申请号：US12114145

申请日：2008-05-02

Applicant: H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

Inventor： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC: H01L23/522

CPC classification number: H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract translation: 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。

公开(公告)号：US07388277B2

公开(公告)日：2008-06-17

申请号：US11033926

申请日：2005-01-12

Applicant: H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

Inventor： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L29/04 ,  H01L31/112 ,  H01L29/40 ,  H01L23/48

CPC classification number: H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract translation: 描述了在芯片级或晶片级的半导体器件集成的过程，其中通过衬底形成垂直连接。 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。

公开(公告)号：US06943106B1

公开(公告)日：2005-09-13

申请号：US10784074

申请日：2004-02-20

Applicant: Kyle K. Kirby ,  Shuang Meng ,  Garo J. Derderian

Inventor： Kyle K. Kirby ,  Shuang Meng ,  Garo J. Derderian

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/4763 ,  H01L21/44

CPC classification number: C23C16/34 ,  C23C16/45525 ,  C23C18/1608 ,  C23C18/1879 ,  C23C18/36 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.

Abstract translation: 一方面，本发明包括制造用于半导体部件的互连的方法。 提供半导体衬底，并且形成完全贯穿衬底的开口。 第一种材料在小于或等于约200℃的温度下沿着开口的侧壁沉积。沉积可以包括原子层沉积和化学气相沉积中的一个或两个，并且第一材料可以包括金属氮化物。 在第一材料的表面上形成焊料润湿材料。 焊料润湿材料可以包括例如镍。 随后，在开口内和焊料润湿材料之上提供焊料。

公开(公告)号：US06599778B2

公开(公告)日：2003-07-29

申请号：US10026103

申请日：2001-12-19

Applicant: H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

Inventor： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC: H01L2100

CPC classification number: H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract translation: 描述了在芯片级或晶片级的半导体器件集成的过程，其中通过衬底形成垂直连接。 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。

公开(公告)号：US20240282747A1

公开(公告)日：2024-08-22

申请号：US18653243

申请日：2024-05-02

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Chandrasekhar Mandalapu ,  Gaius Gillman Fountain, JR. ,  Guilian Gao

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/98 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80895 ,  H01L2224/83009 ,  H01L2224/83896 ,  H01L2224/83948

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

公开(公告)号：US20240194623A1

公开(公告)日：2024-06-13

申请号：US18554923

申请日：2022-03-08

Applicant: TDK ELECTRONICS AG

Inventor： Mehrdad Shayganpoor ,  Guenter Aflenzer ,  Davor Tomassevic ,  Thomas Feichtinger

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/784 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/95 ,  H01L21/784 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/03422 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0529 ,  H01L2224/05339 ,  H01L2224/05347 ,  H01L2224/05548 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/95001 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/1203

Abstract: A semiconductor die and a method for manufacturing a semiconductor die are disclosed. In an embodiment a semiconductor die includes a base body having a semiconductor material and a surface with two contact areas having contact pads at which the semiconductor die is electrically contactable and two metal caps arranged directly at the contact pads.

公开(公告)号：US20240145417A1

公开(公告)日：2024-05-02

申请号：US18205721

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongwoo JIN ,  Myoungchul EUM

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/10 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/02175 ,  H01L2224/0219 ,  H01L2224/03002 ,  H01L2224/0382 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/11002 ,  H01L2224/1182 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27002 ,  H01L2224/27618 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665

Abstract: A semiconductor package and a method of fabricating the same. The semiconductor package includes a lower structure including a first lower conductive pad disposed on an upper surface thereof, a first semiconductor chip disposed on the lower structure, the first semiconductor chip including a first chip conductive pad disposed on a lower surface thereof, a solder ball connecting the first lower conductive pad and the first chip conductive pad, a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip, and a first organic insulating layer covering a side surface of the first chip conductive pad.

公开(公告)号：US20240006352A1

公开(公告)日：2024-01-04

申请号：US18159938

申请日：2023-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： SyuFong LI ,  Yu-Ping TSENG ,  Li-Hsien HUANG ,  Yao-Chun Chuang ,  Yinlung LU

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/80 ,  H01L24/08 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/08145 ,  H01L2224/06517 ,  H01L2224/80379 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2224/80357 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2924/351 ,  H01L2224/0557 ,  H01L24/19 ,  H01L2224/19 ,  H01L24/20 ,  H01L2224/211 ,  H01L2224/214 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0807

Abstract: A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.

公开(公告)号：US11791307B2

公开(公告)日：2023-10-17

申请号：US17209638

申请日：2021-03-23

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Chandrasekhar Mandalapu ,  Gaius Gillman Fountain, Jr. ,  Guilian Gao

IPC: H01L21/683 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/98 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80895 ,  H01L2224/83009 ,  H01L2224/83896 ,  H01L2224/83948

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.