公开(公告)号：US20090059469A1

公开(公告)日：2009-03-05

申请号：US12198342

申请日：2008-08-26

Applicant: Byoung Hwa LEE ,  Sung Kwon WI ,  Hae Suk CHUNG ,  Dong Seok PARK ,  Sang So PARK ,  Min Cheol PARK

Inventor： Byoung Hwa LEE ,  Sung Kwon WI ,  Hae Suk CHUNG ,  Dong Seok PARK ,  Sang So PARK ,  Min Cheol PARK

IPC: H01G4/06 ,  H01G4/228 ,  H05K7/00

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01G4/385 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/09309 ,  H05K2201/09772 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract translation: 本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。 第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极， 并且第一至第四内部电极耦合到第一至第四外部电极。 第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

公开(公告)号：US07491894B2

公开(公告)日：2009-02-17

申请号：US11085342

申请日：2005-03-21

Applicant: Takeshi Suzuki ,  Toshiyuki Ilmura ,  Kazushige Osumi ,  Shinichi Tsuyuki

Inventor： Takeshi Suzuki ,  Toshiyuki Ilmura ,  Kazushige Osumi ,  Shinichi Tsuyuki

IPC: H05K1/16

CPC classification number: H05K1/141 ,  H01L25/16 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0218 ,  H05K1/056 ,  H05K3/284 ,  H05K3/3405 ,  H05K3/3421 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1034 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10977 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A hybrid integrated circuit device of the present invention includes: a circuit board having a front surface subjected to an insulation process; a conductive pattern formed on the front surface of the circuit board; a circuit element placed at a desired position on the conductive pattern and electrically connected to the conductive pattern; and a plurality of leads fixed to the conductive pattern and led to the outside. End portions of the leads which are led to the outside extend approximately parallel to the circuit board in a plane different from that of the front surface of the circuit board.

Abstract translation: 本发明的混合集成电路器件包括：具有经过绝缘处理的正面的电路板; 形成在所述电路板的前表面上的导电图案; 电路元件放置在导电图案上的期望位置并电连接到导电图案; 以及多个引线固定到导电图案并被引导到外部。 引导到外部的引线的端部在与电路板的前表面的平面不同的平面中大致平行于电路板延伸。

公开(公告)号：US07298616B2

公开(公告)日：2007-11-20

申请号：US11369840

申请日：2006-03-08

Applicant: Atsuko Tanaka ,  Masuo Ohnishi

Inventor： Atsuko Tanaka ,  Masuo Ohnishi

IPC: H05K7/20

CPC classification number: H05K1/0272 ,  G06F1/203 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K2201/064 ,  H05K2201/09072 ,  H05K2201/09772 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A fan housing of a fan unit includes a housing wall standing from the surface of a printed circuit board. The printed circuit board serves to establish the fan housing in cooperation with the housing wall. The fan housing further includes a ceiling wall connected to the housing wall. The ceiling wall extends along a datum plane parallel to the surface of the printed circuit board. A high speed airflow can be generated within the fan housing. The airflow promotes the heat radiation from the printed circuit board. An electrically conductive wiring pattern extending over the surface of the printed circuit board may further promote the heat radiation from the printed circuit board.

Abstract translation: 风扇单元的风扇壳体包括从印刷电路板的表面竖立的壳体壁。 印刷电路板用于与壳体壁一起建立风扇壳体。 风扇壳体还包括连接到壳体壁的顶壁。 顶壁沿平行于印刷电路板表面的基准平面延伸。 风扇外壳内可能产生高速气流。 气流促进印刷电路板的热辐射。 在印刷电路板的表面上延伸的导电布线图形可以进一步促进来自印刷电路板的热辐射。

公开(公告)号：US07298028B2

公开(公告)日：2007-11-20

申请号：US11257593

申请日：2005-10-24

Applicant: Chih-Hsiung Lin ,  Nai-Shung Chang

Inventor： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC: H01L23/495

CPC classification number: H05K1/0209 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10734

Abstract: A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

Abstract translation: 一种用于多封装模块（MPM）的封装基板的印刷电路板（PCB）。 PCB包括衬底和其上的散热器。 散热器包括在MPM的封装衬底下方的第一部分。 散热器还包括邻近第一部分的第二部分，包括至少一个散热片。

公开(公告)号：US20070215991A1

公开(公告)日：2007-09-20

申请号：US11308868

申请日：2006-05-17

Applicant: Chyh-Yih Chang ,  Kun-Hsien Tsai

Inventor： Chyh-Yih Chang ,  Kun-Hsien Tsai

IPC: H01L23/495

CPC classification number: H05K1/0218 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/0373 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A tape with a chip-bonding area is provided. The tape is suitable for a chip on film configuration, wherein a chip is suitable for being disposed on the tape and in the chip-bonding area. The tape includes a dielectric base film, a first wiring pattern, and at least a second wiring pattern. The first wiring pattern is disposed on the dielectric base film and has multiple inner leads disposed in the chip-bonding area. The second wiring pattern is disposed on the dielectric base film and in the chip-bonding area. The chip is suitable for being electrically connected to at least a part of the inner leads and being disposed above the second wiring pattern.

Abstract translation: 提供具有芯片接合区域的带。 该胶带适用于胶片配置的芯片，其中芯片适于布置在胶带和芯片粘合区域中。 带包括电介质基底膜，第一布线图案和至少第二布线图案。 第一布线图案设置在电介质基底膜上，并且具有设置在芯片接合区域中的多个内部引线。 第二布线图案设置在电介质基底膜和芯片接合区域中。 该芯片适用于与至少一部分内引线电连接并设置在第二布线图案之上。

公开(公告)号：US07268303B2

公开(公告)日：2007-09-11

申请号：US10682780

申请日：2003-10-09

Applicant: Takeshi Ashida

Inventor： Takeshi Ashida

IPC: H05K1/16

CPC classification number: H01L23/50 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11822 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09772 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a circuit board including a pad for mounting a ball grid array and a wiring, a mounting structure of the ball grid array, an electro-optic device, and an electronic device, the circuit board includes a pad for mounting the ball grid array, a wiring for connecting the pad and an external terminal, and a soldering resist having an opening portion exposing the pad and the wiring.

Abstract translation: 在包括用于安装球栅阵列的焊盘和布线的电路板，球栅阵列的安装结构，电光器件和电子器件中，电路板包括用于安装球栅阵列的焊盘， 用于连接焊盘和外部端子的布线，以及具有露出焊盘和布线的开口部分的焊接抗蚀剂。

公开(公告)号：US20070108628A1

公开(公告)日：2007-05-17

申请号：US11560076

申请日：2006-11-15

Applicant: Takashi Ozawa ,  Yasushi Araki ,  Masatoshi Nakamura ,  Seiji Sato

Inventor： Takashi Ozawa ,  Yasushi Araki ,  Masatoshi Nakamura ,  Seiji Sato

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/73203 ,  H05K3/305 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613

Abstract: A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow of an underfill infiltrated below the semiconductor chip, characterized in that the plurality of dummy patterns are arranged in staggered lattice shape.

Abstract translation: 一种用于以倒装芯片方式安装半导体芯片的安装基板，具有连接半导体芯片的多个连接焊盘，形成为覆盖连接焊盘的一部分的绝缘图案，以及多个用于 控制渗透在半导体芯片下方的底部填充物的流动，其特征在于，所述多个虚拟图案以交错的格子形状布置。

公开(公告)号：US20070057369A1

公开(公告)日：2007-03-15

申请号：US11466843

申请日：2006-08-24

Applicant: Hiroyuki IMAMURA ,  Nozomi SHIMOISHIZAKA

Inventor： Hiroyuki IMAMURA ,  Nozomi SHIMOISHIZAKA

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/005 ,  H05K3/242 ,  H05K2201/09254 ,  H05K2201/09281 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/175 ,  Y02P70/611 ,  H01L2924/00

Abstract: A wiring board includes: an insulating base; a plurality of conductive wirings; and bumps formed on the conductive wirings, respectively. The conductive wirings can be connected with electrode pads of a semiconductor element via the bumps. The conductive wirings include a connection terminal portion at an end portion opposite to the other end portion where the bumps are formed, and at the connection terminal portion, the conductive wirings can be connected with an external component. The conductive wirings include first conductive wirings and second conductive wirings, on which the bumps are formed respectively at a semiconductor element mounting region. The first conductive wirings extend from the bumps to the connection terminal portion. The second conductive wirings extend beyond the semiconductor element mounting region from the bumps but do not reach the connection terminal portion. End portions of the second conductive wirings extending beyond the semiconductor element mounting region are separated electrically from the first conductive wirings by a cutting portion formed at a boundary region with the first conductive wirings. Irrespective of the state of operating electrode pads of a semiconductor element to be mounted, the bumps can be arranged at constant intervals.

Abstract translation: 布线板包括：绝缘基底; 多个导电布线; 和形成在导电配线上的凸块。 导电布线可以通过凸块与半导体元件的电极焊盘连接。 导电布线包括在与形成凸块的另一端部相对的端部处的连接端子部分，并且在连接端子部分处，导电布线可以与外部部件连接。 导电布线包括第一导电布线和第二导电布线，凸块分别形成在半导体元件安装区域上。 第一导电布线从凸块延伸到连接端子部分。 第二导电布线从凸块延伸超出半导体元件安装区域，但不到达连接端子部分。 延伸超过半导体元件安装区域的第二导电配线的端部通过与第一导电布线形成在边界区域处的切割部分与第一导电布线电隔离。 不管要安装的半导体元件的操作电极焊盘的状态如何，可以以恒定的间隔布置凸点。

公开(公告)号：US07078797B2

公开(公告)日：2006-07-18

申请号：US10813137

申请日：2004-03-29

Applicant: Takeshi Suzuki ,  Kazushige Osumi ,  Junichi Ichihashi ,  Toshiyuki Iimura ,  Shinichi Tsuyuki

Inventor： Takeshi Suzuki ,  Kazushige Osumi ,  Junichi Ichihashi ,  Toshiyuki Iimura ,  Shinichi Tsuyuki

IPC: H01L23/48

CPC classification number: H01L24/49 ,  H01L23/4334 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4046 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/09772 ,  H05K2201/10287 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided is a hybrid integrated circuit device which can more effectively stabilize a circuit configured to operate at a high speed. A hybrid integrated circuit device of the embodiment includes a metal substrate provided with an insulating layer on a surface thereof, a conductive pattern formed on a surface of the insulating layer, a semiconductor element fixed onto the conductive pattern, a lead as external connecting means fixed to the conductive pattern in the periphery of the metal substrate, and a contact portion for electrically connecting the conductive pattern electrically connected to the semiconductor element to the metal substrate in the vicinity of the semiconductor element.

Abstract translation: 提供了一种混合集成电路器件，其可以更有效地稳定被配置为高速操作的电路。 本实施例的混合集成电路器件包括在其表面上设置有绝缘层的金属基板，形成在绝缘层的表面上的导电图案，固定到导电图案上的半导体元件，固定的外部连接装置的引线 涉及金属基板周边的导电图案，以及用于将与半导体元件电连接的导电图案与半导体元件附近的金属基板电连接的接触部。

公开(公告)号：US20060038235A1

公开(公告)日：2006-02-23

申请号：US11176782

申请日：2005-07-07

Applicant: Yoshiharu Ogata

Inventor： Yoshiharu Ogata

IPC: H01L29/94

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00014

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。