公开(公告)号：US20090139750A1

公开(公告)日：2009-06-04

申请号：US12318656

申请日：2009-01-05

申请人： Ryo Kanai

发明人： Ryo Kanai

IPC分类号： H05K1/14

CPC分类号： H05K3/4691 ,  H05K1/189 ,  H05K3/3415 ,  H05K3/4611 ,  H05K3/4688 ,  H05K2201/053 ,  H05K2201/055 ,  H05K2203/061 ,  H05K2203/1572

摘要： A printed wiring board has a rigid insulating layer. A first substrate is partly overlaid on the front surface of the rigid insulating layer. The first substrate has a free end located outside the contour of the rigid insulating layer. A second substrate is partly overlaid on the back surface of the rigid insulating layer. The second substrate has a free end located outside the contour of the rigid insulating layer. The second substrate has the front surface opposed to the back surface of the first substrate. A component or components can thus be disposed on the back surface of the first substrate and the front surface of the second substrate outside the contour of the rigid insulating layer. The mounting area for components can be increased.

摘要翻译： 印刷电路板具有刚性绝缘层。 第一基板部分地覆盖在刚性绝缘层的前表面上。 第一衬底具有位于刚性绝缘层轮廓外的自由端。 第二衬底部分覆盖在刚性绝缘层的背面上。 第二基板具有位于刚性绝缘层的轮廓外部的自由端。 第二基板具有与第一基板的背面相对的前表面。 因此，可以在刚性绝缘层的轮廓外的第一基板的背面和第二基板的前表面上设置一个或多个部件。 组件的安装面积可以增加。

公开(公告)号：US20090114433A1

公开(公告)日：2009-05-07

申请号：US12264869

申请日：2008-11-04

申请人： Min Ji KO ,  Eun Tae Park ,  Yong Seok Choi ,  Soo Hyun Lyoo

发明人： Min Ji KO ,  Eun Tae Park ,  Yong Seok Choi ,  Soo Hyun Lyoo

IPC分类号： H05K1/02 ,  H05K3/00

CPC分类号： H05K3/4688 ,  H05K1/0271 ,  H05K1/0306 ,  H05K3/38 ,  H05K3/4629 ,  Y10T29/49124

摘要： There is provided a multi-layered ceramic board and a method of manufacturing the same. A multi-layered ceramic board according to an aspect of the invention may include: an internal layer having a plurality of first dielectric sheets laminated, each of the first dielectric sheets prepared by mixing glass powder with a predetermined amount of alumina powder; and an external layer having at least one second dielectric sheet laminated on the surface of the internal layer, the second dielectric sheet prepared by mixing glass powder with alumina powder in a smaller amount than the first dielectric sheet, wherein via hole conductors and internal electrodes provided in the internal layer are electrically connected to a surface electrode provided on the surface of the external layer, and the internal layer, the external layer, the via hole conductors, the internal layer, and the surface electrode are fired at a predetermined temperature.

摘要翻译： 提供了一种多层陶瓷板及其制造方法。 根据本发明的一个方面的多层陶瓷板可以包括：层叠多个第一电介质片的内层，通过将玻璃粉与预定量的氧化铝粉末混合而制备的每个第一电介质片; 以及外部层，其具有层叠在所述内层的表面上的至少一个第二电介质片，所述第二电介质片通过将玻璃粉末与比所述第一电介质片材更少量的氧化铝粉末混合而制备，其中设置有通孔导体和内部电极 在内层中电连接到设置在外层表面上的表面电极，内部层，外层，通孔导体，内层和表面电极在预定温度下烧制。

公开(公告)号：US07529103B2

公开(公告)日：2009-05-05

申请号：US11438363

申请日：2006-05-23

申请人： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

发明人： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

IPC分类号： H05K1/14

CPC分类号： H05K1/162 ,  H03H7/09 ,  H03H7/1775 ,  H03H2001/0085 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09672

摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

摘要翻译： 嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。 多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。 至少一个电容器是设置在低电介质材料上的叉指电容器。 叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性 。 也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。

公开(公告)号：US20090068426A1

公开(公告)日：2009-03-12

申请号：US12269128

申请日：2008-11-12

申请人： Yoshihiko NISHIZAWA

发明人： Yoshihiko NISHIZAWA

IPC分类号： H01F17/00 ,  B32B18/00 ,  B32B3/10

CPC分类号： H05K3/4688 ,  B32B18/00 ,  C04B35/63 ,  C04B2235/663 ,  C04B2235/9607 ,  C04B2237/32 ,  C04B2237/34 ,  C04B2237/582 ,  C04B2237/68 ,  C04B2237/704 ,  C04B2237/72 ,  H01F17/0006 ,  H01G4/12 ,  H01G4/30 ,  H01G4/40 ,  H01L23/15 ,  H01L23/49822 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/165 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/086 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/24926

摘要： In a multilayer ceramic electronic component, a ceramic laminate is defined by a ceramic base layer and ceramic auxiliary layers arranged on both main surfaces of the ceramic base layer, the ceramic base layer and the ceramic auxiliary layers being co-fired. The ceramic base layer and the ceramic auxiliary layers are made of ferrite materials having substantially the same compositional system and have substantially the same crystal structure. The linear expansion coefficient of the ceramic auxiliary layers is less than the linear expansion coefficient of the ceramic base layer.

摘要翻译： 在多层陶瓷电子部件中，通过陶瓷基底层和布置在陶瓷基底层的两个主表面，陶瓷基底层和陶瓷辅助层上共同烧结的陶瓷辅助层来限定陶瓷层压体。 陶瓷基层和陶瓷辅助层由具有基本上相同的组成系统的铁素体材料制成并且具有基本上相同的晶体结构。 陶瓷辅助层的线膨胀系数小于陶瓷基层的线膨胀系数。

公开(公告)号：US20090011923A1

公开(公告)日：2009-01-08

申请号：US12204006

申请日：2008-09-04

申请人： Tomoyuki Hasegawa ,  Yoshinori Ide ,  Tadashi Otagiri

发明人： Tomoyuki Hasegawa ,  Yoshinori Ide ,  Tadashi Otagiri

IPC分类号： C04B35/468

CPC分类号： H05K1/162 ,  C04B35/4682 ,  C04B35/49 ,  C04B2235/3203 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/3236 ,  C04B2235/3251 ,  C04B2235/3262 ,  C04B2235/3281 ,  C04B2235/3282 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/656 ,  C04B2235/77 ,  H01G4/1227 ,  H01G4/30 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16268 ,  H05K1/0306 ,  H05K3/4688 ,  H05K2201/0187

摘要： The present invention provides a dielectric porcelain composition comprising 100 parts by weight of a barium titanate-based dielectric material and 4 to 10 parts by weight in total of Bi2O3 and at least one compound selected from the group of consisting of CuO, ZnO and MgO.

摘要翻译： 本发明提供一种电介质瓷组合物，其包含100重量份的钛酸钡基电介质材料和4至10重量份的Bi 2 O 3和至少一种选自CuO，ZnO和MgO的化合物。

公开(公告)号：US07468645B2

公开(公告)日：2008-12-23

申请号：US11045936

申请日：2005-01-28

申请人： Takeshi Yamaguchi ,  Toshikazu Imaoka

发明人： Takeshi Yamaguchi ,  Toshikazu Imaoka

IPC分类号： H01P3/08

CPC分类号： H01P3/088 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/024 ,  H05K1/141 ,  H05K3/222 ,  H05K3/28 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/4688 ,  H05K2201/2036 ,  H01L2924/00 ,  H01L2924/00014

摘要： A signal line circuit device is disposed on top of a mounting substrate. The signal line circuit device comprises a dielectric layer, a signal line formed on one surface of the dielectric layer, and a spacer (formed from a solder or a photo solder resist), which is formed between the mounting substrate and the dielectric layer, and generates a space separation between the signal line and the mounting substrate.

摘要翻译： 信号线电路装置设置在安装基板的顶部。 信号线电路装置包括介电层，形成在电介质层的一个表面上的信号线，以及形成在安装基板和电介质层之间的间隔物（由焊料或光阻焊剂形成），以及 在信号线和安装基板之间产生间隔。

公开(公告)号：US07448132B2

公开(公告)日：2008-11-11

申请号：US11537754

申请日：2006-10-02

申请人： Joel R. Goergen

发明人： Joel R. Goergen

IPC分类号： H01K3/10

CPC分类号： H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

摘要： The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.

摘要翻译： 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US20080264677A1

公开(公告)日：2008-10-30

申请号：US11977780

申请日：2007-10-25

申请人： Shih-Ping Hsu

发明人： Shih-Ping Hsu

IPC分类号： H05K1/02 ,  H05K3/30

CPC分类号： H05K1/162 ,  H05K3/107 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09536 ,  H05K2201/09672 ,  Y10T29/49146

摘要： The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability.

摘要翻译： 本发明提供一种具有嵌入式电容器的电路板结构及其制造方法。 电路板结构包括具有至少一个具有非穿透性第一和第二槽的表面的芯层板，分别形成在芯层板的第一和第二槽中的电路层和第一电极板，并且与芯体齐平 层板; 形成在所述芯层基板，所述电路层和所述第一电极板上的高介电材料层; 形成在高电介质材料层上并对应于第一电极板的第二电极板，从而通过第一和第二电极板和高电介质材料层形成电容器。 高介电材料层形成在平面上，以消除填充不良，提高可靠性。

公开(公告)号：US20080236877A1

公开(公告)日：2008-10-02

申请号：US11732174

申请日：2007-04-02

申请人： Daniel I. Amey ,  William Borland

发明人： Daniel I. Amey ,  William Borland

IPC分类号： H05K1/16 ,  H05K3/30

CPC分类号： H05K1/162 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/3011 ,  H05K1/114 ,  H05K1/141 ,  H05K3/4688 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/4913 ,  H01L2224/0401

摘要： A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively and wherein the first and second electrode of the singulated capacitor is interconnected to the first and second electrode respectively of an external planar capacitor embedded within a printed wiring motherboard.

摘要翻译： 一种包括功率核心的装置，其中所述功率核心包括：至少一个嵌入式单电容器，其中所述嵌入式单电容器包括至少第一电极和第二电极，并且其中所述嵌入式单电容器位于功率核心的外层上， 半导体器件的至少一个Vcc（功率）端子和至少一个Vss（接地）端子可以分别直接连接到至少一个第一和至少一个第二电极，并且其中所述单个电容器的第一和第二电极 分别与嵌入印刷布线母板内的外部平面电容器的第一和第二电极互连。

公开(公告)号：US20080178999A1

公开(公告)日：2008-07-31

申请号：US11872942

申请日：2007-10-16

申请人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

发明人： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC分类号： B32B37/04

CPC分类号： H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.