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111 条记录 (耗时 0.033 秒)

    Method of fabricating a flip-chip ball-grid-array package with molded underfill
    82.
    发明授权
    Method of fabricating a flip-chip ball-grid-array package with molded underfill 有权
    制造具有模制底部填充物的倒装芯片球栅阵列封装的方法

    公开(公告)号：US06451625B1

    公开(公告)日：2002-09-17

    申请号：US09760440

    申请日：2001-01-13

    申请人： Han-Ping Pu ,  Tzong-Da Ho

    发明人： Han-Ping Pu ,  Tzong-Da Ho

    IPC分类号： H01L2144

    CPC分类号： H01L21/563 ,  H01L24/28 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A method of fabricating a FCBGA (Flip-Chip Bal-Grid-Array) package with molded underfill is proposed, which is characterized by the forming of a mold-buffering opening in the solder mask at the exit of the vent hole in the substrate, wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole, so that during molding process when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the mold-buffering opening, thereby preventing it from flashing to nearby solder-ball pads. Since there would substantially exist no mold flash over the exposed surface of the solder mask and the solder-ball pads, the resulted FCBGA package would be assured in the quality of its outer appearance and the bonding between the solder-ball pads and the subsequently attached solder balls thereon.

    摘要翻译： 提出了一种制造具有模制底部填充物的FCBGA（倒装芯片平行栅格阵列）封装的方法，其特征在于在衬底中的通气孔的出口处在焊料掩模中形成模具缓冲开口， 其特征在于，所述模具缓冲口的尺寸设定为比所述通气孔的内径大的宽度，使得在所述密封材料渗透到所述通气孔的出口的成型工序中，所述密封材料可以被限制在所述模具缓冲开口 从而防止其闪烁到附近的焊球垫。 由于在焊接掩模和焊球垫的暴露表面上基本上不存在模具闪光，所以将确保所得到的FCBGA封装的外观质量和焊球垫与随后附着的粘合 焊球上。

    Die carrier for package on package assembly
    86.
    发明授权
    Die carrier for package on package assembly 有权
    封装组件上的封装的载体

    公开(公告)号：US08927333B2

    公开(公告)日：2015-01-06

    申请号：US13302059

    申请日：2011-11-22

    申请人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

    发明人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

    IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L23/48 ,  H01L23/552 ,  H01L25/10

    CPC分类号： H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012

    摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

    摘要翻译： 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

    Wafer level chip scale package with reduced stress on solder balls
    89.
    发明授权
    Wafer level chip scale package with reduced stress on solder balls 有权
    晶圆级芯片级封装，焊球应力减小

    公开(公告)号：US08373282B2

    公开(公告)日：2013-02-12

    申请号：US13162394

    申请日：2011-06-16

    申请人： Yu-Feng Chen ,  Yu-Ling Tsai ,  Han-Ping Pu ,  Hung-Jui Kuo ,  Yu Yi Huang

    发明人： Yu-Feng Chen ,  Yu-Ling Tsai ,  Han-Ping Pu ,  Hung-Jui Kuo ,  Yu Yi Huang

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/562 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

    摘要： A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

    摘要翻译： 一种结构包括半导体衬底上的金属焊盘，具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层，其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。 后钝化互连（PPI）包括在第一聚酰亚胺层之上的第一部分，以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。 第二个聚酰亚胺层位于PPI之上。 第二聚酰亚胺层具有第二厚度和第二杨氏模量。 厚度比和杨氏模量比中的至少一个大于1.0，其中厚度比是第一厚度与第二厚度的比率，杨氏模量比是第二杨氏模量与第一杨氏模量之比 模数。

    Semiconductor device and fabrication methods thereof
    90.
    发明授权
    Semiconductor device and fabrication methods thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US07888236B2

    公开(公告)日：2011-02-15

    申请号：US11798432

    申请日：2007-05-14

    申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

    发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

    摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

    摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。