公开(公告)号：US20060191638A1

公开(公告)日：2006-08-31

申请号：US10906627

申请日：2005-02-28

申请人： Timothy Dalton ,  Emily Gallagher ,  Louis Kindt ,  Carey Thiel ,  Andrew Watts

发明人： Timothy Dalton ,  Emily Gallagher ,  Louis Kindt ,  Carey Thiel ,  Andrew Watts

IPC分类号： C23F1/00 ,  C23C16/00

CPC分类号： H01J37/32706 ,  H01J37/32091 ,  H01J37/32541

摘要： An apparatus (and method for operating the same) which allows etching different substrate etch areas of a substrate having different pattern densities at essentially the same etch rate. The apparatus includes (a) a chamber; (b) an anode and a cathode in the chamber; and (c) a bias power system coupled to the cathode, wherein the cathode includes multiple cathode segments. The operation method includes the steps of: (i) placing a substrate to be etched between the anode and cathode, wherein the substrate includes N substrate etch areas, and the N substrate etch areas are directly above the N cathode segments; (ii) determining N bias powers which, when being applied to the N cathode segments during an etching of the substrate, will result in essentially a same etch rate for the N substrate etch areas; and (iii) using the bias power system to apply the N bias powers the N cathode segments.

摘要翻译： 一种用于以基本上相同的蚀刻速率蚀刻具有不同图案密度的衬底的不同衬底蚀刻区域的装置（及其操作方法）。 该装置包括（a）室; （b）室中的阳极和阴极; 和（c）耦合到所述阴极的偏置功率系统，其中所述阴极包括多个阴极段。 操作方法包括以下步骤：（i）将待蚀刻的衬底放置在阳极和阴极之间，其中衬底包括N个衬底蚀刻区域，并且N个衬底蚀刻区域直接在N个阴极段的上方; （ii）确定N偏压功率，当在衬底的蚀刻期间施加到N个阴极段时，将产生对于N个衬底蚀刻区域基本上相同的蚀刻速率; 和（iii）使用偏置电力系统对N个阴极段施加N个偏置功率。

公开(公告)号：US20060166416A1

公开(公告)日：2006-07-27

申请号：US10905938

申请日：2005-01-27

申请人： Timothy Dalton ,  Wesley Natzle ,  Paul Pastel ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Timothy Dalton ,  Wesley Natzle ,  Paul Pastel ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/32139 ,  H01L21/32137 ,  Y10S438/909

摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

摘要翻译： 一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。 使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。 压载气体可以类似于或等同于在处理室内产生的气态副产物。 压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。 这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。 当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。 钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

公开(公告)号：US20060154086A1

公开(公告)日：2006-07-13

申请号：US11034480

申请日：2005-01-13

申请人： Nicholas Fuller ,  Stephen Gates ,  Timothy Dalton

发明人： Nicholas Fuller ,  Stephen Gates ,  Timothy Dalton

IPC分类号： B32B17/06 ,  B32B9/00 ,  H01L21/302

CPC分类号： H01L21/0331 ,  H01L21/76811 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/31667 ,  H01L2924/00

摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

摘要翻译： 具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。 本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。 后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20050127514A1

公开(公告)日：2005-06-16

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Timothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Timothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US20050037608A1

公开(公告)日：2005-02-17

申请号：US10639989

申请日：2003-08-13

申请人： Panayotis Andricacos ,  Emanuel Cooper ,  Timothy Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Kwietniak ,  Michelle Steen ,  Cornelia Tsang

发明人： Panayotis Andricacos ,  Emanuel Cooper ,  Timothy Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Kwietniak ,  Michelle Steen ,  Cornelia Tsang

IPC分类号： H01L21/288 ,  H01L21/3065 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/30655 ,  H01L21/76898

摘要： Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

摘要翻译： 提供具有约2或更大的纵横比的扩张和未扩口的金属化深通孔。 盲孔已经在硅衬底中制造达到约300微米的深度，并且通过通孔已经被制造高达约750微米，硅衬底晶片的大致厚度，使得能够在两端或两端形成电连接 的通道。 尽管可以获得深度和高纵横比，但是蚀刻的通孔完全被电镀铜导体填充，从而形成深通孔并允许更充分地使用基板的两侧。

公开(公告)号：US08421126B2

公开(公告)日：2013-04-16

申请号：US13164173

申请日：2011-06-20

申请人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L27/085

CPC分类号： H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 半导体结构。 半导体结构包括两个绝缘体上硅晶片，其中制造了器件，并且利用掩埋氧化物层将它们背靠背接合，或者使用衬底间介质层和掩埋氧化物层之间的结合层将它们背靠背连接。 这些结构包括形成在上晶片中的触点与下晶片中的器件和形成在上晶片上的布线电平。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07989312B2

公开(公告)日：2011-08-02

申请号：US12612957

申请日：2009-11-05

申请人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07497959B2

公开(公告)日：2009-03-03

申请号：US10709514

申请日：2004-05-11

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： H01B3/00 ,  H01L21/31 ,  H01L49/00

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

摘要翻译： 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US07462509B2

公开(公告)日：2008-12-09

申请号：US11383595

申请日：2006-05-16

申请人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

摘要： An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

摘要翻译： 一种封装电子设备的方法。 用于封装器件的方法包括：提供第一衬底，第二衬底和具有第一侧和相对第二侧的集成电路芯片，第一组芯片焊盘和第二组芯片焊盘， 集成电路芯片的第二侧，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的相应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。