公开(公告)号：US20140322932A1

公开(公告)日：2014-10-30

申请号：US13870938

申请日：2013-04-25

Applicant: Donald T. Tran ,  Rajasekaran Swaminathan

Inventor： Donald T. Tran ,  Rajasekaran Swaminathan

IPC: H01R13/627 ,  H01R13/652 ,  H01R4/48

CPC classification number: H01R12/721 ,  H01R12/714 ,  H01R12/81 ,  H01R13/6581 ,  H01R13/6592 ,  H01R43/205 ,  Y10T29/49174 ,  Y10T29/49176

Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例涉及包括边缘指状连接器以及相关联的配置和方法的互连电缆。 边缘指状连接器可以设置在互连电缆的第一端处，并且可以将互连电缆连接到包括在封装衬底中或耦合到封装衬底的边缘指状物。 封装衬底可以包括在处理器封装组件中，并且处理器可以安装在衬底上。 互连电缆可以包括一个或多个细长导体，其中触点直接耦合到相应的导体。 第二连接器可以设置在互连电缆的第二端处，并且可以将互连电缆耦合到被配置为将互连电缆连接到SFP电缆的小型可插拔（SFP）壳体。 可以描述和要求保护其他实施例。

公开(公告)号：US20150118870A1

公开(公告)日：2015-04-30

申请号：US14065281

申请日：2013-10-28

Applicant: Rajasekaran Swaminathan ,  Ram S. Viswanath ,  Sanka Ganesan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley ,  Vijaykumar Krithivasan ,  David J. Llapitan ,  Neal E. Ulen ,  Donald T. Tran

Inventor： Rajasekaran Swaminathan ,  Ram S. Viswanath ,  Sanka Ganesan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley ,  Vijaykumar Krithivasan ,  David J. Llapitan ,  Neal E. Ulen ,  Donald T. Tran

IPC: H01R12/71 ,  H01R43/00

CPC classification number: H05K7/10 ,  H01R12/00 ,  H01R12/716 ,  H01R13/2442 ,  H05K1/00 ,  Y10T29/49169

Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.

Abstract translation: 描述了与集成电路（IC）连接器相关的实施例。 在一些实施例中，IC组件可以包括IC封装衬底，中间构件和阳连接器。 IC封装基板可以在顶表面或底表面上具有第一信号触点，并且底表面可以具有用于与电路板上的插座耦合的第二信号触点。 中间构件可以具有联接到第一信号触头的第一端和延伸超过侧表面的第二端。 阳连接器可以设置在中间构件的第二端处，并且可以具有联接到中间构件的信号触点的信号触点。 当阴连接器沿平行于中间构件的轴线的方向接合时，阳连接器可与母连接器配合。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20150318630A1

公开(公告)日：2015-11-05

申请号：US14269795

申请日：2014-05-05

Applicant: Donald T. Tran ,  Srikant Nekkanty ,  Rajasekaran Swaminathan

Inventor： Donald T. Tran ,  Srikant Nekkanty ,  Rajasekaran Swaminathan

IPC: H01R12/73

CPC classification number: H01R12/732 ,  H01R12/714 ,  H01R12/721

Abstract: A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a first slot configured to receive and permit horizontal displacement of an edge finger of a second board relative thereto, while a second connector defines a second slot configured to receive and permit horizontal displacement of an edge finger of a first board relative thereto, to thereby establish an electrical connection between the first board and the second board.

Abstract translation: 双配合边缘指状连接器，其被配置为使连接器密度加倍，而不需要减小间距。 第一连接器限定配置成接收并允许第二板相对于其的边缘指状物的水平位移的第一槽，而第二连接器限定第二槽，其构造成接收和允许第一板相对于其的边缘手指的水平位移 ，从而在第一板和第二板之间建立电连接。

公开(公告)号：US20160044786A1

公开(公告)日：2016-02-11

申请号：US14456606

申请日：2014-08-11

Applicant: Rajasekaran Swaminathan ,  Sairam Agraharam ,  Amruthavalli Pallavi Alur ,  Ram Viswanath ,  Wei-Lun Kane Jen

Inventor： Rajasekaran Swaminathan ,  Sairam Agraharam ,  Amruthavalli Pallavi Alur ,  Ram Viswanath ,  Wei-Lun Kane Jen

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/40 ,  H01L23/00

CPC classification number: H05K1/112 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16501 ,  H01L2224/29082 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81464 ,  H01L2224/83101 ,  H01L2224/83191 ,  H05K1/09 ,  H05K1/113 ,  H05K1/185 ,  H05K3/243 ,  H05K3/244 ,  H05K3/4046 ,  H05K2201/09472 ,  H05K2201/10189 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079

Abstract: This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.

Abstract translation: 本公开一般涉及电子封装和方法，其包括导电焊盘，包括基本上不导电的材料的封装绝缘体层，封装绝缘体层基本上是平面的，以及通孔。 通孔可以形成在封装绝缘体层内并电耦合到导电焊盘。 通孔可以包括垂直延伸穿过封装绝缘体层的至少一部分并且具有靠近导电焊盘的第一端和与第一端相对的第二端和固定到导体的第二端的光洁度层的导体， 层包括金化合物。

公开(公告)号：US08939347B2

公开(公告)日：2015-01-27

申请号：US12768842

申请日：2010-04-28

Applicant: Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

Inventor： Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

IPC: B23K31/02 ,  B23K35/12 ,  H01L23/498 ,  B82Y25/00 ,  H01L23/00

CPC classification number: H01L23/49816 ,  B82Y25/00 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13211 ,  H01L2224/13239 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/81805

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.

Abstract translation: 本公开涉及制造微电子封装的领域，其中分布在焊膏内的磁性颗粒可用于形成磁性金属间化合物互连。 金属间化合物互连可以暴露于磁场，磁场可以将焊料材料加热到回流温度，以附接包括微电子封装的微电子部件。

公开(公告)号：US08287996B2

公开(公告)日：2012-10-16

申请号：US12653791

申请日：2009-12-21

Applicant: Dingying Xu ,  Leonel R. Arana ,  Nachiket R. Raravikar ,  Mohit Mamodia ,  Rajasekaran Swaminathan ,  Rahul Manepalli

Inventor： Dingying Xu ,  Leonel R. Arana ,  Nachiket R. Raravikar ,  Mohit Mamodia ,  Rajasekaran Swaminathan ,  Rahul Manepalli

IPC: B32B27/32

CPC classification number: H01L23/3737 ,  H01L24/81 ,  H01L2924/12042 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/265 ,  Y10T428/3154 ,  H01L2924/00

Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.

Abstract translation: 用于微电子器件的涂层包括含有填料（232）的聚合物膜（131）。 聚合物膜的热导率大于3W / m·K，厚度（133）不超过10微米。 聚合物膜可以与切割带（310）组合以形成简化微电子封装（100）的制造工艺的处理（300），并且可以使用该处理（300）来管理微电子器件的热分布。

公开(公告)号：US20110291276A1

公开(公告)日：2011-12-01

申请号：US12787968

申请日：2010-05-26

Applicant: Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

Inventor： Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

IPC: H01L29/40 ,  H01L21/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.

Abstract translation: 本公开涉及制造微电子封装的领域，其中微电子封装的微电子部件可以具有包括烧结金属和磁性颗粒的烧结导电通孔。

公开(公告)号：US20110159228A1

公开(公告)日：2011-06-30

申请号：US12655366

申请日：2009-12-29

Applicant: Rajasekaran Swaminathan ,  Hong Dong ,  Sandeep Razdan ,  Nisha Ananthakrishana ,  Rahul Manepalli

Inventor： Rajasekaran Swaminathan ,  Hong Dong ,  Sandeep Razdan ,  Nisha Ananthakrishana ,  Rahul Manepalli

IPC: B32B5/16 ,  B05D5/00 ,  C08L63/00

CPC classification number: H01L23/293 ,  C08L63/00 ,  H01L21/563 ,  H01L24/29 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81911 ,  H01L2924/14 ,  Y10T428/23 ,  Y10T428/25 ,  Y10T428/259 ,  Y10T428/31529 ,  Y10T428/31678 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/05442 ,  H01L2924/0665

Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.

Abstract translation: 描述形成底部填充材料的方法和相关结构。 这些方法可以包括将底部填充物施加到包含来自不干净焊剂的残余物的互连结构，其中底部填充物包括官能化纳米填料和微米级填料中的至少一种。

公开(公告)号：US07906376B2

公开(公告)日：2011-03-15

申请号：US12164996

申请日：2008-06-30

Applicant: Rajasekaran Swaminathan

Inventor： Rajasekaran Swaminathan

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L23/10 ,  H01L23/295 ,  H01L23/367 ,  H01L23/42 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83222 ,  H01L2224/8385 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.

Abstract translation: 描述半导体封装。 半导体封装包括设置在基板上方并与基板耦合的集成散热器。 空腔设置在基板和集成散热器之间。 半导体管芯设置在衬底上方和空腔中。 在衬底和半导体管芯之间设置一系列一级焊点。 一层磁性颗粒基复合材料也设置在空腔中。

公开(公告)号：US20140175644A1

公开(公告)日：2014-06-26

申请号：US13721329

申请日：2012-12-20

Applicant: Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

Inventor： Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括将装置附接到贴片基板，其中组装的装置和贴片基板包括翘曲，将组装的装置和贴片基板附接到插入件以形成封装结构，然后在温度下回流封装结构 低于大约200摄氏度以形成基本平坦的包装结构。