Abstract:
Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.
Abstract:
Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.
Abstract:
Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.
Abstract:
A SATA-compatible storage controller that can be configured to allow computers assigned to multiple different computer domains connected by at least one switch fabric to share resources of a common set of storage devices. The storage controller includes a plurality of virtual storage controllers, each providing an interface to a respective computer domain connected to the switch fabric, a virtualization mechanism configured to implement link layer virtualization for the common set of storage devices, and a split serial advanced technology attachment (SATA) protocol stack, the processing of which is partitioned between the respective virtual storage controllers and the virtualization mechanism.
Abstract:
All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.
Abstract:
All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.
Abstract:
Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.
Abstract:
Methods and apparatus for implementing a mode-switch protocol and mechanism for hybrid wireless display system with screencasting and native graphics throwing. Under a Mircast implementation, A Wi-Fi Direct (WFD) link is established between WFD source and sink devices, with the WFD source device configured to operate as a Miracast source that streams Miracast content to a Miracast sink that is configured to operate on the WFD sink device using a Miracast mode. The WFD source and sink devices are respectively configured as a native graphics thrower and catcher and support operation in a native graphics throwing mode, wherein the WFD source devices throw at least one of native graphics commands and native graphics content to the WFD sink device. In response to detection that Miracast content has been selected to be played on the WFD source device, the operating mode is switched to the Miracast mode. The mode may also be automatically or selectively switched back to the native graphics throwing mode. The techniques may also be applied to methods and apparatus that support other types of screencasting techniques and both wireless and wired links.
Abstract:
Impeller architecture for a cooling fan and methodology for making same. The impeller architecture includes a plurality of blades, individual ones of the blades have a first end that is attached to a hub component in a sequential order, such that sequential first ends are attached to the circumference. An indexing function is applied to the sequential order, and blades or the spaces therebetween are modified accordingly to have a blade type based on their sequential location and the indexing function. The indexing function can be, in a non-limiting example, odd numbers or prime numbers.
Abstract:
Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.