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1.发明授权Semiconductor device and method of bonding different size semiconductor die at the wafer level 有权半导体器件和在晶圆级接合不同尺寸的半导体管芯的方法公开(公告)号：US08993377B2
公开(公告)日：2015-03-31
申请号：US13231839
申请日：2011-09-13
申请人： Jun Mo Koo , Pandi C. Marimuthu , Seung Wook Yoon , Il Kwon Shim
发明人： Jun Mo Koo , Pandi C. Marimuthu , Seung Wook Yoon , Il Kwon Shim
IPC分类号： H01L21/56 , H01L25/07 , H01L23/00 , H01L21/683 , H01L21/768 , H01L25/065 , H01L23/31 , H01L25/10
CPC分类号： H01L24/96 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3107 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68327 , H01L2221/68381 , H01L2221/68386 , H01L2224/0231 , H01L2224/02313 , H01L2224/02317 , H01L2224/02372 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/14181 , H01L2224/16146 , H01L2224/1703 , H01L2224/17181 , H01L2224/21 , H01L2224/2105 , H01L2224/215 , H01L2224/22 , H01L2224/221 , H01L2224/29144 , H01L2224/2919 , H01L2224/48105 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73259 , H01L2224/73265 , H01L2224/81005 , H01L2224/81815 , H01L2224/831 , H01L2224/95001 , H01L2224/96 , H01L2225/06513 , H01L2225/06541 , H01L2225/1052 , H01L2225/1058 , H01L2924/00 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/81 , H01L2924/01014 , H01L2924/0665 , H01L2924/01028 , H01L2924/3512 , H01L2924/00012
摘要： A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
摘要翻译： 半导体晶片具有第一和第二相对表面。 多个导电通孔部分地形成在半导体晶片的第一表面上。 将半导体晶片分割成多个第一半导体管芯。 第一半导体管芯安装到载体上。 第二半导体管芯安装到第一半导体管芯。 第二半导体管芯的占地面积大于第一半导体管芯的占地面积。 密封剂沉积在第一和第二半导体管芯和载体上。 载体被移除。 去除第二表面的一部分以暴露导电通孔。 在与第二半导体管芯相对的第一半导体管芯的表面上形成互连结构。 或者，第一密封剂沉积在第一半导体管芯和载体上，并且第二密封剂沉积在第二半导体管芯上。
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2.发明申请Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level 有权半导体器件及其在晶片级接合不同尺寸半导体晶片的方法公开(公告)号：US20120074587A1
公开(公告)日：2012-03-29
申请号：US13231839
申请日：2011-09-13
申请人： Jun Mo Koo , Pandi C. Marimuthu , Seung Wook Yoon , Il Kwon Shim
发明人： Jun Mo Koo , Pandi C. Marimuthu , Seung Wook Yoon , Il Kwon Shim
CPC分类号： H01L24/96 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3107 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68327 , H01L2221/68381 , H01L2221/68386 , H01L2224/0231 , H01L2224/02313 , H01L2224/02317 , H01L2224/02372 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/14181 , H01L2224/16146 , H01L2224/1703 , H01L2224/17181 , H01L2224/21 , H01L2224/2105 , H01L2224/215 , H01L2224/22 , H01L2224/221 , H01L2224/29144 , H01L2224/2919 , H01L2224/48105 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73259 , H01L2224/73265 , H01L2224/81005 , H01L2224/81815 , H01L2224/831 , H01L2224/95001 , H01L2224/96 , H01L2225/06513 , H01L2225/06541 , H01L2225/1052 , H01L2225/1058 , H01L2924/00 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/81 , H01L2924/01014 , H01L2924/0665 , H01L2924/01028 , H01L2924/3512 , H01L2924/00012
摘要： A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
摘要翻译： 半导体晶片具有第一和第二相对表面。 多个导电通孔部分地形成在半导体晶片的第一表面上。 将半导体晶片分割成多个第一半导体管芯。 第一半导体管芯安装到载体上。 第二半导体管芯安装到第一半导体管芯。 第二半导体管芯的占地面积大于第一半导体管芯的占地面积。 密封剂沉积在第一和第二半导体管芯和载体上。 载体被移除。 去除第二表面的一部分以暴露导电通孔。 在与第二半导体管芯相对的第一半导体管芯的表面上形成互连结构。 或者，第一密封剂沉积在第一半导体管芯和载体上，并且第二密封剂沉积在第二半导体管芯上。
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3.发明申请Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer 有权半导体器件和形成具有半导体晶片的TSV插入件的方法和内插器的相对表面上的建立互连结构公开(公告)号：US20120074585A1
公开(公告)日：2012-03-29
申请号：US13184253
申请日：2011-07-15
CPC分类号： H01L21/76898 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81192 , H01L2224/81201 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/83
摘要： A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.
摘要翻译： 半导体器件具有带有第一和第二相对表面的衬底。 多个导电通孔部分地形成在衬底的第一表面上。 在与导电通孔电连接的基板的第一表面上形成第一导电层。 第一半导体管芯安装在衬底的第一表面上。 第一半导体管芯和衬底安装到载体上。 密封剂沉积在第一半导体管芯，衬底和载体上。 去除衬底的第二表面的一部分以露出导电通孔。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 第二半导体管芯可以堆叠在第一半导体管芯上。 第二半导体管芯可以安装在与第一半导体管芯相邻的衬底的第一表面上。
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4.发明授权Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer 有权半导体器件和在内插器的相对表面上形成具有半导体管芯和堆积互连结构的TSV插入器的方法公开(公告)号：US09224647B2
公开(公告)日：2015-12-29
申请号：US13184253
申请日：2011-07-15
IPC分类号： H01L23/48 , H01L21/56 , H01L21/768 , H01L21/48 , H01L23/14 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/18
CPC分类号： H01L21/76898 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81192 , H01L2224/81201 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/83
摘要： A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.
摘要翻译： 半导体器件具有带有第一和第二相对表面的衬底。 多个导电通孔部分地形成在衬底的第一表面上。 在与导电通孔电连接的基板的第一表面上形成第一导电层。 第一半导体管芯安装在衬底的第一表面上。 第一半导体管芯和衬底安装到载体上。 密封剂沉积在第一半导体管芯，衬底和载体上。 去除衬底的第二表面的一部分以露出导电通孔。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 第二半导体管芯可以堆叠在第一半导体管芯上。 第二半导体管芯可以安装在与第一半导体管芯相邻的衬底的第一表面上。
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5.发明授权Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices 失效用于Cu /低/超低k器件的聚合物封装切割通道（PEDL）技术公开(公告)号：US07160756B2
公开(公告)日：2007-01-09
申请号：US10963285
申请日：2004-10-12
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L23/3185 , H01L23/3192 , H01L24/05 , H01L24/11 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05567 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/45144 , H01L2224/48463 , H01L2224/48599 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/05552 , H01L2224/05556 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer layer comprised with a low dielectric constant is applied. After definition of openings in the first photosensitive polymer layer exposing portions of the top surface of the copper interconnect structures, a dicing lane opening is defined in materials located between copper interconnect structures. Conductive redistribution shapes are formed on the copper interconnect structures exposed in the openings in the first photosensitive polymer layer, followed by application of a protective, second photosensitive polymer layer. An opening is defined in the second photosensitive polymer layer exposing a portion of the top surface of a redistribution shape followed by placement of a solder ball in this opening. A reflow anneal procedure results in the solder ball wetting and overlying only the portion of the redistribution shape exposed in the opening in the second photosensitive polymer layer. Separation of the solder ball, flip chip regions from the non-solder ball, wire bond regions is accomplished via a dicing procedure performed in the dicing lane.
摘要翻译： 已经开发了用于封装用于倒装芯片和引线接合应用的半导体器件的方法，其中半导体器件的特定材料在器件处理序列和切割过程中被保护。 在由低k绝缘体层围绕的铜互连结构的定义之后，施加包含低介电常数的保护性第一光敏聚合物层。 在第一感光聚合物层中限定出露出铜互连结构的顶表面的部分的开口之后，在位于铜互连结构之间的材料中限定切割通道开口。 导电再分布形状形成在暴露在第一光敏聚合物层的开口中的铜互连结构上，随后施加保护性的第二光敏聚合物层。 在第二感光聚合物层中限定开口，暴露再分布形状的顶表面的一部分，然后在该开口中放置焊球。 回流退火程序导致焊球润湿，并且仅覆盖暴露在第二感光聚合物层中的开口中的再分布形状的部分。 通过在切割车道中执行的切割程序来实现焊球，倒装芯片区域与非焊球，引线键合区域的分离。
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