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公开(公告)号：US20120322255A1
公开(公告)日：2012-12-20
申请号：US13161303
申请日：2011-06-15
申请人： Ming-Da Cheng , Chih-Wei Lin , Hsiu-Jen Lin , Tzong-Hann Yang , Wen-Hsiung Lu , Zheng-Yi Lim , Yi-Wen Wu , Chung-Shi Liu
发明人： Ming-Da Cheng , Chih-Wei Lin , Hsiu-Jen Lin , Tzong-Hann Yang , Wen-Hsiung Lu , Zheng-Yi Lim , Yi-Wen Wu , Chung-Shi Liu
IPC分类号： H01L21/768
CPC分类号： H01L24/11 , H01L21/6836 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2221/68327 , H01L2224/11003 , H01L2224/111 , H01L2224/1133 , H01L2224/11462 , H01L2224/1147 , H01L2224/11825 , H01L2224/11849 , H01L2224/119 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13655 , H01L2224/13671 , H01L2224/13672 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81193 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01083 , H01L2924/0103 , H01L2924/01047 , H01L2924/01082 , H01L2224/11
摘要： A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.
摘要翻译： 提供一种用于形成金属凸块的系统和方法。 一个实施例包括将导电材料附着到载体介质上，然后将导电材料接触到基底的导电区域。 然后使用接合工艺将导电材料的部分结合到导电区域，以在导电区域上形成导电盖，并且去除残留的导电材料和载体介质。 回流工艺用于将导电盖重新流到导电凸块中。
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公开(公告)号：US08501615B2
公开(公告)日：2013-08-06
申请号：US13161303
申请日：2011-06-15
申请人： Ming-Da Cheng , Chih-Wei Lin , Hsiu-Jen Lin , Tzong-Hann Yang , Wen-Hsiung Lu , Zheng-Yi Lim , Yi-Wen Wu , Chung-Shi Liu
发明人： Ming-Da Cheng , Chih-Wei Lin , Hsiu-Jen Lin , Tzong-Hann Yang , Wen-Hsiung Lu , Zheng-Yi Lim , Yi-Wen Wu , Chung-Shi Liu
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L21/6836 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2221/68327 , H01L2224/11003 , H01L2224/111 , H01L2224/1133 , H01L2224/11462 , H01L2224/1147 , H01L2224/11825 , H01L2224/11849 , H01L2224/119 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13655 , H01L2224/13671 , H01L2224/13672 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81193 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01083 , H01L2924/0103 , H01L2924/01047 , H01L2924/01082 , H01L2224/11
摘要： A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.
摘要翻译： 提供一种用于形成金属凸块的系统和方法。 一个实施例包括将导电材料附着到载体介质上，然后将导电材料接触到基底的导电区域。 然后使用接合工艺将导电材料的部分结合到导电区域，以在导电区域上形成导电盖，并且去除残留的导电材料和载体介质。 回流工艺用于将导电盖重新流到导电凸块中。
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公开(公告)号：US08242011B2
公开(公告)日：2012-08-14
申请号：US13004376
申请日：2011-01-11
申请人： Zheng-Yi Lim , Yi-Wen Wu , Wen-Hsiung Lu , Chih-Wei Lin , Tzong-Huann Yang , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
发明人： Zheng-Yi Lim , Yi-Wen Wu , Wen-Hsiung Lu , Chih-Wei Lin , Tzong-Huann Yang , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05647 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/1147 , H01L2224/1181 , H01L2224/11824 , H01L2224/11827 , H01L2224/11849 , H01L2224/1308 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/13583 , H01L2224/13693 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/12044 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/01073 , H01L2924/01049 , H01L2924/0103 , H01L2924/01025 , H01L2924/01022 , H01L2924/01032 , H01L2924/01078 , H01L2924/01012 , H01L2924/01013 , H01L2924/0104 , H01L2924/01046 , H01L2924/01082 , H01L2924/01029 , H01L2924/01083 , H01L2924/01051 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar.
摘要翻译： 本公开涉及制造金属柱。 制造半导体器件的示例性方法包括以下步骤：提供具有接触焊盘的衬底; 形成在所述衬底上延伸的钝化层，所述钝化层在所述接触焊盘上具有开口; 在所述接触焊盘和所述钝化层的一部分上形成金属柱; 在金属柱上形成焊料层; 并且使金属柱的侧壁与有机化合物反应，以在金属柱的侧壁上形成自组装单层或有机化合物的自组装多层。
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公开(公告)号：US20130181338A1
公开(公告)日：2013-07-18
申请号：US13349405
申请日：2012-01-12
申请人： Wen-Hsiung Lu , Yi-Wen Wu , Chih-Wei Lin , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
发明人： Wen-Hsiung Lu , Yi-Wen Wu , Chih-Wei Lin , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L23/498 , H01L21/20
CPC分类号： H01L23/3192 , H01L21/56 , H01L21/568 , H01L23/3114 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02331 , H01L2224/03823 , H01L2224/0401 , H01L2224/05007 , H01L2224/05008 , H01L2224/05082 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/05548 , H01L2224/05564 , H01L2224/05567 , H01L2224/05611 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/10126 , H01L2224/11464 , H01L2224/1191 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/73104 , H01L2924/00014 , H01L2924/181 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.
摘要翻译： 一种结构包括形成在半导体衬底上的后钝化互连层，形成在后钝化互连层上的金属凸块和形成在半导体衬底上的模塑复合层。 金属凸块的下部嵌入在模塑料层中，并且金属凸块的中间部分被凹弯月面模塑料保护层包围。
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公开(公告)号：US09607921B2
公开(公告)日：2017-03-28
申请号：US13349405
申请日：2012-01-12
申请人： Wen-Hsiung Lu , Yi-Wen Wu , Chih-Wei Lin , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
发明人： Wen-Hsiung Lu , Yi-Wen Wu , Chih-Wei Lin , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00
CPC分类号： H01L23/3192 , H01L21/56 , H01L21/568 , H01L23/3114 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02331 , H01L2224/03823 , H01L2224/0401 , H01L2224/05007 , H01L2224/05008 , H01L2224/05082 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/05548 , H01L2224/05564 , H01L2224/05567 , H01L2224/05611 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/10126 , H01L2224/11464 , H01L2224/1191 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/73104 , H01L2924/00014 , H01L2924/181 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.
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6.发明授权Forming wafer-level chip scale package structures with reduced number of seed layers 有权形成具有减少种子层数的晶片级芯片级封装结构公开(公告)号：US08735273B2
公开(公告)日：2014-05-27
申请号：US13179299
申请日：2011-07-08
申请人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L21/566 , H01L21/76885 , H01L23/3114 , H01L23/3157 , H01L23/525 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/0346 , H01L2224/0347 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05552 , H01L2224/05567 , H01L2224/05655 , H01L2224/05664 , H01L2224/11334 , H01L2224/11849 , H01L2224/1191 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
摘要： A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.
摘要翻译： 一种方法包括在覆盖半导体衬底的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。
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7.发明申请Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers 有权形成具有减少种子层数的晶片级芯片级封装结构公开(公告)号：US20130009307A1
公开(公告)日：2013-01-10
申请号：US13179299
申请日：2011-07-08
申请人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/03 , H01L21/566 , H01L21/76885 , H01L23/3114 , H01L23/3157 , H01L23/525 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/0346 , H01L2224/0347 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05552 , H01L2224/05567 , H01L2224/05655 , H01L2224/05664 , H01L2224/11334 , H01L2224/11849 , H01L2224/1191 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
摘要： A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.
摘要翻译： 一种方法包括在覆盖在半导体衬底上的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。
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公开(公告)号：US08884431B2
公开(公告)日：2014-11-11
申请号：US13228768
申请日：2011-09-09
申请人： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu , Meng-Tse Chen , Chun-Cheng Lin , Yu-Peng Tsai , Kuei-Wei Huang , Wei-Hung Lin
发明人： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu , Meng-Tse Chen , Chun-Cheng Lin , Yu-Peng Tsai , Kuei-Wei Huang , Wei-Hung Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/683 , H01L23/498 , H01L21/56 , H01L25/065 , H01L23/538 , H01L25/00 , H01L23/00 , H01L23/31 , H01L25/10 , H01L25/03 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/52 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2221/68331 , H01L2221/68345 , H01L2221/68377 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/06515 , H01L2224/09181 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/73259 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2924/14 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15322 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2224/81 , H01L2224/03 , H01L2924/014 , H01L2924/00
摘要： Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
摘要翻译： 公开了用于半导体器件的封装方法和结构。 在一个实施例中，封装的半导体器件包括具有第一表面和与第一表面相对的第二表面的再分配层（RDL）。 至少一个集成电路耦合到RDL的第一表面，并且多个金属凸块耦合到RDL的第二表面。 模制化合物设置在RDL的至少一个集成电路和第一表面上。
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公开(公告)号：US20120299181A1
公开(公告)日：2012-11-29
申请号：US13118108
申请日：2011-05-27
申请人： Meng-Tse Chen , Wei-Hung Lin , Sheng-Yu Wu , Chun-Cheng Lin , Kuei-Wei Huang , Yu-Peng Tsai , Chih-Wei Lin , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Ming-Da Cheng , Chung-Shi Liu
发明人： Meng-Tse Chen , Wei-Hung Lin , Sheng-Yu Wu , Chun-Cheng Lin , Kuei-Wei Huang , Yu-Peng Tsai , Chih-Wei Lin , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/17 , H01L21/565 , H01L21/566 , H01L23/3114 , H01L23/3128 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/16055 , H01L2224/16113 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/1023 , H01L2225/1058 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/1304 , H01L2924/14 , H01L2924/1432 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/00
摘要： A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.
摘要翻译： 包装方法包括将包装部件放置在脱模膜上，其中包装部件表面上的焊球与剥离膜物理接触。 接下来，填充在剥离膜和包装部件之间的模塑料固化，其中在固化步骤期间，焊球与剥离膜保持物理接触。
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公开(公告)号：US20130062761A1
公开(公告)日：2013-03-14
申请号：US13228768
申请日：2011-09-09
申请人： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu , Meng-Tse Chen , Chun-Cheng Lin , Yu-Peng Tsai , Kuei-Wei Huang , Wei-Hung Lin
发明人： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu , Meng-Tse Chen , Chun-Cheng Lin , Yu-Peng Tsai , Kuei-Wei Huang , Wei-Hung Lin
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/52 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2221/68331 , H01L2221/68345 , H01L2221/68377 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/06515 , H01L2224/09181 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/73259 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2924/14 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15322 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2224/81 , H01L2224/03 , H01L2924/014 , H01L2924/00
摘要： Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
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