公开(公告)号：US20150001707A1

公开(公告)日：2015-01-01

申请号：US13930980

申请日：2013-06-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Asri Yusof

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3121 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49433 ,  H01L2224/83191 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a surface of the base between the conductive posts. An interconnect structure is formed over the semiconductor die and conductive posts. An adhesive layer is disposed over the semiconductor die. A conductive layer is disposed over the adhesive layer. An encapsulant is deposited over the semiconductor die and around the conductive posts. One or more conductive posts are electrically isolated from the substrate. The conductive layer is a removable or sacrificial cap layer. The substrate includes a wafer-shape, panel, or singulated form. The semiconductor die is disposed below a height of the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts.

Abstract translation: 半导体器件具有包括基底和从基底延伸的多个导电柱的基底。 半导体管芯设置在导电柱之间的基座的表面上。 在半导体管芯和导电柱上形成互连结构。 粘合剂层设置在半导体管芯上。 导电层设置在粘合剂层上。 密封剂沉积在半导体管芯上并且在导电柱周围。 一个或多个导电柱与衬底电隔离。 导电层是可移除或牺牲的盖层。 基板包括晶片形状，面板或单切形式。 半导体管芯设置在导电柱的高度的下方。 在半导体管芯，密封剂和导电柱上形成互连结构。

公开(公告)号：US20150279815A1

公开(公告)日：2015-10-01

申请号：US14228769

申请日：2014-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Sung Soo Kim

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01082 ,  H01L2224/81805 ,  H01L2224/45099

Abstract: A semiconductor device has a first conductive layer disposed over a carrier. A second conductive layer is formed over a first surface of the first conductive layer. A first insulating layer is formed over the first and second conductive layers. A third conductive layer is formed over the first insulating layer. A second insulating layer is formed over the third conductive layer. The carrier is removed to expose the first conductive layer. A portion of the first conductive layer is removed from a second surface of the first conductive layer opposite the first surface to form a plurality of conductive pillars. The conductive pillars include a height of 100 micrometers or greater. The portion of the first conductive layer is removed using an etching process. The conductive pillars are disposed over a first semiconductor package. A semiconductor die or second semiconductor package is disposed over the second conductive layer.

Abstract translation: 半导体器件具有设置在载体上的第一导电层。 在第一导电层的第一表面上形成第二导电层。 在第一和第二导电层上形成第一绝缘层。 在第一绝缘层上形成第三导电层。 在第三导电层上形成第二绝缘层。 移除载体以露出第一导电层。 第一导电层的一部分从与第一表面相对的第一导电层的第二表面去除以形成多个导电柱。 导电柱包括100微米或更大的高度。 使用蚀刻工艺去除第一导电层的部分。 导电柱设置在第一半导体封装之上。 半导体管芯或第二半导体封装设置在第二导电层上。

公开(公告)号：US20130241030A1

公开(公告)日：2013-09-19

申请号：US13886556

申请日：2013-05-03

Applicant: STATS CHIPPAC, LTD.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

Abstract translation: 半导体器件具有形成在基底基板的第一表面中的凹部的基底基板。 第一导电层形成在第一表面上并进入凹槽中。 在基底基板的第二表面上形成第二导电层。 第一半导体管芯安装到基底基板上，凸起部分设置在第一导电层的凹槽内。 第二半导体管芯安装到第一半导体管芯。 在第二半导体管芯和第一导电层之间的基底衬底的第一表面上形成接合线。 密封剂沉积在第一和第二半导体管芯和基底衬底上。 基底基板的一部分从第二导电层之间的第二表面移除到凹部，以形成用于凸块和接合线的电隔离的基底引线。

公开(公告)号：US09449932B2

公开(公告)日：2016-09-20

申请号：US13886556

申请日：2013-05-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L24/14 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

公开(公告)号：US09368423B2

公开(公告)日：2016-06-14

申请号：US13930980

申请日：2013-06-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Asri Yusof

IPC: H01L23/52 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49433 ,  H01L2224/83191 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a surface of the base between the conductive posts. An interconnect structure is formed over the semiconductor die and conductive posts. An adhesive layer is disposed over the semiconductor die. A conductive layer is disposed over the adhesive layer. An encapsulant is deposited over the semiconductor die and around the conductive posts. One or more conductive posts are electrically isolated from the substrate. The conductive layer is a removable or sacrificial cap layer. The substrate includes a wafer-shape, panel, or singulated form. The semiconductor die is disposed below a height of the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts.

Abstract translation: 半导体器件具有包括基底和从基底延伸的多个导电柱的基底。 半导体管芯设置在导电柱之间的基座的表面上。 在半导体管芯和导电柱上形成互连结构。 粘合剂层设置在半导体管芯上。 导电层设置在粘合剂层上。 密封剂沉积在半导体管芯上并且在导电柱周围。 一个或多个导电柱与衬底电隔离。 导电层是可移除或牺牲的盖层。 基板包括晶片形状，面板或单切形式。 半导体管芯设置在导电柱的高度的下方。 在半导体管芯，密封剂和导电柱上形成互连结构。