公开(公告)号：US20070088451A1

公开(公告)日：2007-04-19

申请号：US11545067

申请日：2006-10-06

Applicant: Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

Inventor： Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

IPC: G06F19/00

CPC classification number: G03F7/7065 ,  G06F11/006 ,  H01L2223/5444

Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

Abstract translation: 在集成电路（IC）制造过程中的创造性方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修理，包括将数据与每个的熔丝ID相关联地存储 IC。 IC的ID代码在制造过程中例如在打开/短路测试中自动读取。 然后访问与IC的ID代码相关联存储的数据，并且根据所访问的数据选择IC可能经历的附加修复过程。 因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

公开(公告)号：US20070069372A1

公开(公告)日：2007-03-29

申请号：US11603581

申请日：2006-11-22

Applicant: Salman Akram ,  James Wark

Inventor： Salman Akram ,  James Wark

IPC: H01L23/34

CPC classification number: H01L24/85 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/83951 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00011 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

Abstract translation: 一种通过在其上放置形成球顶部的一部分的散热材料在半导体芯片的上表面上提供散热器的装置和方法。 该装置包括附接到衬底并与衬底电连通的半导体芯片。 将阻挡球顶部材料施加到与附接到基板的表面相对的表面（“相对表面”）上的半导体芯片的边缘，以形成围绕半导体芯片的相对表面的周边的壁，其中阻挡球顶部 材料也延伸到接触并粘附到基底上。 围绕半导体芯片的相对表面的周边的壁形成凹部。 散热球形材料设置在凹部内以接触半导体芯片的相对表面。

公开(公告)号：US20060261340A1

公开(公告)日：2006-11-23

申请号：US11494453

申请日：2006-07-28

Applicant: Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

Inventor： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

IPC: H01L29/04 ,  H01L33/00 ,  H01L29/768 ,  H01L27/148 ,  H01L31/0203

CPC classification number: H01L27/14618 ,  H01L23/481 ,  H01L24/48 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract translation: 本文公开了微电子成像器和用于封装微电子成像器的方法。 在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。 导电晶片互连延伸穿过管芯并且与焊盘接触。 互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。 导电支撑构件由接合垫承载和突出。 图像传感器上的盖连接到支撑构件。

公开(公告)号：US20050275048A1

公开(公告)日：2005-12-15

申请号：US10867352

申请日：2004-06-14

Applicant: Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

Inventor： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/48 ,  H01L27/14 ,  H01L27/146 ,  H01L31/00 ,  H01L31/0203 ,  H01L31/0232

CPC classification number: H01L27/14618 ,  H01L23/481 ,  H01L24/48 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract translation: 本文公开了微电子成像器和用于封装微电子成像器的方法。 在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。 导电晶片互连延伸穿过管芯并且与焊盘接触。 互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。 导电支撑构件由接合垫承载和突出。 图像传感器上的盖连接到支撑构件。

公开(公告)号：US20110233777A1

公开(公告)日：2011-09-29

申请号：US13154550

申请日：2011-06-07

Applicant: Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

Inventor： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20070017093A1

公开(公告)日：2007-01-25

申请号：US11528137

申请日：2006-09-27

Applicant: James Wark ,  Salman Akram

Inventor： James Wark ,  Salman Akram

IPC: H01R43/00

CPC classification number: H01R12/57 ,  G01R1/0408 ,  G01R1/0466 ,  H01L2924/0002 ,  H01R43/205 ,  H05K1/119 ,  H05K3/325 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09472 ,  H05K2201/10689 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49179 ,  Y10T29/49222 ,  Y10T29/49453 ,  H01L2924/00

Abstract: A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads as close as desired to the body of the chip package. Moreover, the contact structures can be adapted for making contact with leads having a very fine pitch. In one embodiment, the contact structures include raised members formed over a body of the interposer. A conductive layer is formed over each of the raised members to provide a contact surface for engaging the leads of the chip package. In another embodiment, the raised members are replaced with depressions formed into the interposer. A conductive layer is formed on an inside surface of each depression to provide a contact surface for engaging the leads of the chip package. Any combination of raised members and depressions may be used.

Abstract translation: 一种制造具有用于与芯片封装的引线暂时电接触的接触结构阵列的插入件的方法。 接触结构可以使引线接近芯片封装体的所需位置。 此外，接触结构可以适于与具有非常细的间距的引线接触。 在一个实施例中，接触结构包括形成在插入件的主体上的凸起部件。 在每个凸起构件上形成导电层，以提供用于接合芯片封装引线的接触表面。 在另一个实施例中，凸起构件被形成在插入件中的凹陷所代替。 在每个凹陷的内表面上形成导电层，以提供用于接合芯片封装的引线的接触表面。 可以使用凸起构件和凹陷的任何组合。

公开(公告)号：US20060060968A1

公开(公告)日：2006-03-23

申请号：US11269053

申请日：2005-11-08

Applicant: James Wark ,  Salman Akram

Inventor： James Wark ,  Salman Akram

IPC: H01L23/48

CPC classification number: H01L24/10 ,  G01R1/06738 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/12 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10734 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are arranged to make electrical contact with the solder balls of a bumped IC device without substantially deforming the solder ball. Accordingly, reflow of solder balls to reform the solder balls is not necessary with the contact pad of the present invention. Such a contact pad may be provided on various testing equipment such as probes and the like and may be used for both temporary and permanent connections. Also disclosed is an improved method of forming the contact pads by etching and deposition.

公开(公告)号：US20060046088A1

公开(公告)日：2006-03-02

申请号：US10934635

申请日：2004-09-02

Applicant: Salman Akram ,  James Wark ,  William Hiatt

Inventor： Salman Akram ,  James Wark ,  William Hiatt

IPC: H01L29/12

CPC classification number: H01L21/76879 ,  C23C18/1607 ,  C23C18/1637 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/34 ,  C23C18/36 ,  H01L21/288 ,  H01L21/76898 ,  H01L2924/00013 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2224/29099

Abstract: A method of selectively plating nickel on an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device structure having at least one aluminum or copper structure and at least one tungsten structure. One of the aluminum or copper structure and the tungsten structure is nickel plated while the other remains unplated. The aluminum or copper structure or the tungsten structure may first be activated toward nickel plating. The activated aluminum or copper structure or the activated tungsten structure may then be nickel plated by immersing the intermediate semiconductor device structure in an electroless nickel plating solution. The unplated aluminum or copper structure or the unplated tungsten structure may subsequently be nickel plated by activating the unplated structure and nickel plating the activated structure. A method of simultaneously plating the aluminum or copper structure and the tungsten structure with nickel is also disclosed, as is an intermediate semiconductor device structure.

Abstract translation: 在中间半导体器件结构上选择性镀镍的方法。 该方法包括提供具有至少一个铝或铜结构和至少一个钨结构的中间半导体器件结构。 铝或铜结构之一和钨结构是镀镍的，而另一个保持未镀层。 可以首先将铝或铜结构或钨结构活化成镀镍。 然后可以通过将中间半导体器件结构浸入无电镀镍溶液中来将活化的铝或铜结构或活化的钨结构镀镍。 然后通过激活未镀层的结构和镀镍活化的结构，可以将未镀覆的铝或铜结构或未镀覆的钨结构镀镍。 还公开了一种用镍同时电镀铝或铜结构和钨结构的方法，以及中间半导体器件结构。

公开(公告)号：US20060011809A1

公开(公告)日：2006-01-19

申请号：US10894262

申请日：2004-07-19

Applicant: Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Alan Wood ,  Peter Benson ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Charles Watkins ,  Salman Akram

Inventor： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Alan Wood ,  Peter Benson ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Charles Watkins ,  Salman Akram

IPC: H01L27/00

CPC classification number: H01L27/00 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/00014

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

公开(公告)号：US20100171217A1

公开(公告)日：2010-07-08

申请号：US12725724

申请日：2010-03-17

Applicant: Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

Inventor： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC: H01L23/498

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。