公开(公告)号：US11211339B2

公开(公告)日：2021-12-28

申请号：US16703468

申请日：2019-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chuei-Tang Wang ,  Vincent Chen ,  Tzu-Chun Tang ,  Chen-Hua Yu ,  Ching-Feng Yang ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Kai-Chiang Wu ,  Shou Zen Chang ,  Wei-Ting Lin ,  Chun-Lin Lu

IPC: H01L23/58 ,  H01L23/552 ,  H01L21/78 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.

公开(公告)号：US10727082B2

公开(公告)日：2020-07-28

申请号：US14839047

申请日：2015-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shou Zen Chang ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Ching-Feng Yang ,  Vincent Chen ,  Chuei-Tang Wang ,  Yen-Ping Wang ,  Hsien-Wei Chen ,  Wei-Ting Lin

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

公开(公告)号：US10109605B2

公开(公告)日：2018-10-23

申请号：US14742398

申请日：2015-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Hsiang Chuang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Kai-Chiang Wu ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  H01L23/495 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L23/31

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

公开(公告)号：US09806045B2

公开(公告)日：2017-10-31

申请号：US14014051

申请日：2013-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hao-Yi Tsai

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06051 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/14051 ,  H01L2224/16058 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3512

Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

公开(公告)号：US09627325B2

公开(公告)日：2017-04-18

申请号：US13787630

申请日：2013-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Kai Liu ,  Chia-Chun Miao ,  Kai-Chiang Wu ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Yen-Ping Wang ,  Chun-Lin Lu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/544 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/10165 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

公开(公告)号：US20170098640A1

公开(公告)日：2017-04-06

申请号：US15380821

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Liang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Ching-Feng Yang ,  Ming-Kai Liu ,  Chia-Chun Miao

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/522 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/065 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2224/80815 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/92124 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/186 ,  H05K3/4682 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

公开(公告)号：US20140353819A1

公开(公告)日：2014-12-04

申请号：US13907875

申请日：2013-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Hsiang Chuang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Kai-Chiang Wu ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/495 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49568 ,  H01L23/522 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/06515 ,  H01L2224/06519 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13455 ,  H01L2224/13464 ,  H01L2224/16225 ,  H01L2224/17515 ,  H01L2224/17519 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract translation: 集成电路结构包括金属焊盘，包括金属焊盘上的部分的钝化层，钝化层上的第一聚合物层和延伸到第一聚合物层的第一钝化互连（PPI）。 第一PPI电连接到金属垫。 虚设金属垫位于第一聚合物层中。 第二聚合物层覆盖第一聚合物层，虚拟金属垫和第一PPI。 欠冲击冶金（UBM）延伸到第二聚合物层中以电耦合到虚拟金属垫。

公开(公告)号：US11101238B2

公开(公告)日：2021-08-24

申请号：US15926266

申请日：2018-03-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Kai Liu ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Yen-Ping Wang ,  Chia-Chun Miao

IPC: H01L23/00

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

公开(公告)号：US10950556B2

公开(公告)日：2021-03-16

申请号：US16569876

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Ching-Feng Yang ,  Meng-Tse Chen

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/66 ,  H01L21/3205 ,  H01L21/288 ,  H01L23/00 ,  H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L25/10 ,  H01L21/78 ,  H01L25/065

Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.

公开(公告)号：US10269588B2

公开(公告)日：2019-04-23

申请号：US15152308

申请日：2016-05-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Liang ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Ching-Feng Yang ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Yen-Ping Wang

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.