公开(公告)号：US20120206160A1

公开(公告)日：2012-08-16

申请号：US13025931

申请日：2011-02-11

申请人： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

发明人： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

IPC分类号： G01R31/00

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.

摘要翻译： 提供用于对一个或多个微丸下的装置进行电测试的测试结构。 每个测试结构包括至少一个微型块和测试垫。 微型焊盘是与设备的互连件连接的金属焊盘的一部分。 微型焊盘的宽度等于或小于约50μm。 测试垫连接到至少一个微型块。 测试垫的尺寸足够大以允许设备的电路探测。 测试垫是金属垫的另一部分。 测试垫的宽度大于至少一个微小块垫。

公开(公告)号：US20110291288A1

公开(公告)日：2011-12-01

申请号：US12787661

申请日：2010-05-26

申请人： Wei-Cheng WU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU

发明人： Wei-Cheng WU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU

IPC分类号： H01L23/538

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/11002 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684

摘要： A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure.

摘要翻译： 封装系统包括设置在插入件上的集成电路。 插入器包括第一互连结构。 第一衬底设置在第一互连结构之上。 第一衬底包括其中的至少一个第一至硅通孔（TSV）结构。 模制复合材料设置在第一互连结构上并且围绕第一基板。 集成电路与至少一个第一TSV结构电耦合。

公开(公告)号：US20130147032A1

公开(公告)日：2013-06-13

申请号：US13313747

申请日：2011-12-07

申请人： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

发明人： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

摘要翻译： 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US20130009317A1

公开(公告)日：2013-01-10

申请号：US13178079

申请日：2011-07-07

申请人： Chi-Chun HSIEH ,  Wei-Cheng WU ,  Hsiao-Tsung YEN ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG

发明人： Chi-Chun HSIEH ,  Wei-Cheng WU ,  Hsiao-Tsung YEN ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L23/481 ,  H01L21/743 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

摘要翻译： 形成插入件的方法包括提供半导体衬底，该半导体衬底具有与前表面相对的前表面和后表面; 形成从所述前表面延伸到所述半导体衬底中的一个或多个穿硅通孔（TSV）; 形成覆盖所述半导体衬底的前表面和所述一个或多个TSV的层间介电层（ILD）层; 以及在所述ILI层中形成互连结构，所述互连结构将所述一个或多个TSV电连接到所述半导体衬底。

公开(公告)号：US20120061823A1

公开(公告)日：2012-03-15

申请号：US12879512

申请日：2010-09-10

申请人： Wei-Cheng WU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Chao-Wen Shih

发明人： Wei-Cheng WU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Chao-Wen Shih

IPC分类号： H01L23/498 ,  H01L23/485 ,  H01L23/482 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0235 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/06131 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/35 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

摘要翻译： 半导体器件具有在金属焊盘和凸块下金属化（UBM）层之间具有环形应力缓冲层的焊盘结构。 应力缓冲层由介电常数小于3.5的介质层，聚合物层或铝层形成。 应力缓冲层是圆形环，方形环，八角形环或任何其它几何环。

公开(公告)号：US20130320493A1

公开(公告)日：2013-12-05

申请号：US13485340

申请日：2012-05-31

申请人： Chun Hua CHANG ,  Der-Chyang YEH ,  Kuang-Wei CHENG ,  Yuan-Hung LIU ,  Shang-Yun HOU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

发明人： Chun Hua CHANG ,  Der-Chyang YEH ,  Kuang-Wei CHENG ,  Yuan-Hung LIU ,  Shang-Yun HOU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

IPC分类号： H01L21/02 ,  H01L29/02

CPC分类号： H01L28/40 ,  H01L21/02 ,  H01L21/768 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/53295 ,  H01L28/60 ,  H01L29/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.

摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在插入器中形成通孔，并且在下层金属化层和较高级金属化层之间形成电容器。 电容器可以是例如具有双电容器电介质层的平面电容器。

公开(公告)号：US20090032945A1

公开(公告)日：2009-02-05

申请号：US12244699

申请日：2008-10-02

申请人： Shin-Puu JENG ,  Hao-Yi TSAI ,  Shang-Yun HOU ,  Hsien-Wei CHEN ,  Chia-Lun TSAI

发明人： Shin-Puu JENG ,  Hao-Yi TSAI ,  Shang-Yun HOU ,  Hsien-Wei CHEN ,  Chia-Lun TSAI

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块具有其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸点还具有在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。