公开(公告)号：EP1635625A2

公开(公告)日：2006-03-15

申请号：EP04258036.5

申请日：2004-12-22

Applicant: FUJITSU LIMITED

Inventor： Koide, Masateru c/o Fujitsu Ltd

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/18 ,  H05K3/38 ,  H01L21/48

CPC classification number: H01L23/50 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/381 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/10636 ,  H05K2203/0228 ,  Y02P70/611

Abstract: A laminating step includes a second step of laminating a second insulation layer (30) on a conductive pattern last formed at a first step, roughening the surface (30a) of the laminated second insulation layer (30) excluding a desired area (S=302), and forming a conductive layer (21) on at least the desired area (S), and forming a third insulating layer (60) on at least the desired area (S) of the surface of the second insulation layer (30), and a processing step includes a removing step of removing an upper part (R) of the area higher than the second insulation layer (30) on the substrate obtained at the laminating step, and an exposing step of exposing a part (25) of the area of a conductive pattern adjacent to the lower side of the second insulation layer (30).

Abstract translation: 层压步骤包括：第二步骤，将第二绝缘层（30）层叠在最后形成于第一步骤的导电图案上，使层压的第二绝缘层（30）的表面（30a）粗糙化，除去期望的面积（S = 302 ），并且在至少所需区域（S）上形成导电层（21），并且在所述第二绝缘层（30）的表面的至少所需区域（S）上形成第三绝缘层（60） 并且处理步骤包括去除在层压步骤获得的基板上的高于第二绝缘层（30）的区域的上部（R）的去除步骤，以及暴露步骤， 与第二绝缘层（30）的下侧相邻的导电图案的区域。

公开(公告)号：EP0971570A4

公开(公告)日：2006-01-04

申请号：EP98901002

申请日：1998-01-23

Applicant: IBIDEN CO LTD

Inventor： TAKADA MASARU ,  TSUKADA KIYOTAKA ,  KOBAYASHI HIROYUKI ,  MINOURA HISASHI ,  UKAI YOSHIKAZU ,  KONDO MITSUHIRO

IPC: B23K26/00 ,  H01L21/48 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: When a printed wiring board which has inner layer conductor circuits (161 and 131) between insulating layers (101 - 103) and blind via-holes (141 and 142) made from the top surface of the insulating layer to the inner layer conductor circuits is manufactured, a hole (160) is provided beforehand in the center part of the inner layer conductor circuits (161) at the bottom of the blind via-hole (141), and a laser beam is applied from the top surface side of the insulating layer to form the blind via-holes (141 and 142). After that, metal plating films are formed on the surfaces of the inner layer conductor circuits (131 and 161) and the blind via-holes (141 and 142).

Abstract translation: 一种制造印刷电路板（210）的方法，包括由合成树脂制成的至少两个绝缘层（211,212,213），布置在绝缘层之间的内层导体电路（221-225）和多个盲孔（ 3A-3E），其由最外表面朝向内层导体电路（221-225）形成，并且通过在形成盲通孔（3A-3E）的每一部分上依次照射激光束而具有不同的深度，其特征在于，最浅盲 通过使用具有形成标准孔所需的能量强度的标准激光束（242）将通孔（3A-3E）形成为标准孔，并且将标准激光束（242）多次照射 形成具有更深深度的盲孔（3B，3D，3E）。

公开(公告)号：EP1030366B1

公开(公告)日：2005-10-19

申请号：EP00102116.1

申请日：2000-02-04

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Kimbara, Hidenori, Mitsubishi Gas Chem. Co., Inc. ,  Ikeguchi, Nobuyuki, Mitsubishi Gas Chem. Co., Inc. ,  Komatsu, Katsuji, Mitsubishi Gas Chem. Co., Inc.

IPC: H01L23/32 ,  H01L23/498

CPC classification number: H01L24/45 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/40252 ,  H05K1/0373 ,  H05K1/112 ,  H05K3/0038 ,  H05K3/3436 ,  H05K3/4629 ,  H05K2201/0209 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/613 ,  Y10T428/24917 ,  Y10T428/31681 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2224/45099 ,  H01L2224/43

Abstract: Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The printed wiring board has, as a substrate for a chip scale package, a double-side copper-clad laminate formed of an insulation layer and having copper foils on both surfaces, wherein the double-side copper-clad laminate has an upper copper foil surface and a lower copper foil surface, the upper copper foil surface has a wire bonding or flip chip bonding terminal and has a copper pad in a position where the copper pad can be electrically connected to said wire bonding or flip chip bonding terminal and can be connected to a blind via hole formed in the lower copper surface, the lower copper foil surface has a solder-balls-fixing pad in a position corresponding to said copper pad, the solder-balls-fixing pad has at least 2 blind via holes within itself, and the solder-balls-fixing pad connected to a reverse surface of the copper pad with a conductive material is electrically connected with solder balls which are melted and filled in blind via holes so as to be mounded.

公开(公告)号：EP1567979A1

公开(公告)日：2005-08-31

申请号：EP03780100.8

申请日：2003-12-02

Applicant: Mühlbauer AG

Inventor： RIED, Michael ,  BRUNNER, Anton

IPC: G06K19/077

CPC classification number: G06K19/0775 ,  G06K19/07745 ,  G06K19/07749 ,  H01L2924/0002 ,  H05K1/183 ,  H05K3/321 ,  H05K2201/0314 ,  H05K2201/09472 ,  H05K2201/10727 ,  H01L2924/00

Abstract: The invention relates to a chipcard and a method for production of such a chipcard with a card body (11), at least one recess (12a, 12b), arranged therein for housing at least one chip module (16), with module connections (17) in the boundary region (16a) of the chip module (16) and a conducting structure body with body contact connections (13), embedded in the card body (11), in particular, an antenna with antenna connections which are arranged beneath the boundary region (16a) of the chip module (16). The assembled chip module (16) is arranged between the module connections (17) and the body contact connections (13) by means of adhesive pieces (14), preferably applied at points, made from elastic conducting material with application of pressure to produce a contact between the connections (13, 17).

公开(公告)号：EP1523229A3

公开(公告)日：2005-07-27

申请号：EP04025133.2

申请日：1999-06-30

Applicant: FormFactor, Inc.

Inventor： Pedersen, David V. ,  Eldridge, Benjamin N. ,  Khandros, Igor Y.

IPC: H05K3/32 ,  G01R1/04

CPC classification number: G01R1/0466 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements (516), such as spring contact elements, extending from electronic components (518), such as semiconductor devices. Socket substrates (504) are provided with capture pads (506) for receiving ends of elongate interconnection elements (516) extending from electronic components (518). Various capture pad configurations are disclosed. A securing device such as a housing (520) positions the electronic component securely to the socket substrate (504). Connections to external devices are provided via conductive traces (510) adjacent the surface of the socket substrate. The socket substrate (504) may be supported by a support substrate (502). In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

公开(公告)号：EP1397031A3

公开(公告)日：2005-01-19

申请号：EP03023330.8

申请日：1996-09-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro ,  Mori, Yoji

IPC: H01L23/12 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

公开(公告)号：EP1392089A1

公开(公告)日：2004-02-25

申请号：EP02255849.8

申请日：2002-08-21

Applicant: Ultratera Corporation

Inventor： Maa, Chong-Ren ,  Chih, Wan-Kuo ,  Tsou, Ching-Hua

IPC: H05K1/11 ,  H05K3/34 ,  H01L21/60

CPC classification number: H01L24/16 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K1/112 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/09981 ,  H05K2201/10674 ,  H05K2203/054 ,  H01L2224/0401

Abstract: A printed circuit board (PCB), which has bonding pads (21) thereon for mounting a flip chip, comprises a substrate (10) having a conductor pattern (20), which is composed of a plurality of traces in a specific layout. A solder mask (30) is provided on the substrate (10) sheltering the conductor pattren (20). The solder mask (30) is provided with vias (31) to expose the conductor pattern (20) at predetermined portions, and pad layers (40) are provided on the side walls of the vias (31) of the solder mask (30) respectively and are electrically connected with the conductor pattern (20) at the portions exposed via the vias (31) respectively to form the bonding pads (21) of the printed circuit board. Such that when the flip chip (70) has solder bump (71) injected into the bonding pads (21), the solder bumps (71) will be filled therein and fixedly connected with the pad layers (40) to couple the flip chip (70) with the PCB in a fixedly status.

Abstract translation: 在其上具有用于安装倒装芯片的接合焊盘（21）的印刷电路板（PCB）包括具有导体图案（20）的基板（10），其由特定布局的多个迹线组成。 在基板（10）上设置有阻挡导体板（20）的焊接掩模（30）。 焊接掩模（30）设置有通孔（31）以在预定部分露出导体图案（20），并且焊盘层（40）设置在焊接掩模（30）的通孔（31）的侧壁上， 分别在通过通孔（31）暴露的部分处与导体图案（20）电连接以形成印刷电路板的接合焊盘（21）。 使得当倒装芯片（70）具有注入到焊盘（21）中的焊料凸点（71）时，焊料凸块（71）将被填充在其中并与焊盘层（40）固定连接，以将倒装芯片（ 70），PCB处于固定状态。

公开(公告)号：EP1035580A3

公开(公告)日：2003-12-03

申请号：EP00301805.8

申请日：2000-03-06

Applicant: Altera Corporation

Inventor： Anderson, Sidney Larry ,  Long, Jon ,  Fritz, Donald S.

IPC: H01L23/498 ,  H01L21/58 ,  H01L23/31

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An integrated circuit package is constructed to potential reduce stress and damage to an integrated circuit die. A rigid transition medium (42) is attached using adhesive layers (38,40) and interfaces between a tape carrier (20) and the integrated circuit die (18). The integrated circuit package prevents damage such as die cracks and also enhances the service life of the packaged integrated circuit part.

公开(公告)号：EP1205971A3

公开(公告)日：2003-01-02

申请号：EP01126395.1

申请日：2001-11-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Yasuda, Masao ,  Sumikawa, Masato

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/10234 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/013

Abstract: An electronic component having an electrode structure to increase an allowance positional deviation in a mounting process as well as a method and a structure for mounting a semiconductor device are provided. The semiconductor device (5) includes, on electrodes (4), connection materials (3, 9) connecting the semiconductor device (5) and a substrate (6). The connection materials include a composite connection material (9) formed of a core (1) and a conductor (2) covering the core, the core having an a low modulus of elasticity at room temperature smaller than that of the conductor at room temperature, and a single-layer connection material (3) formed of a conductor.

Abstract translation: 提供一种具有电极结构的电子部件，其具有用于增加安装过程中的容许位置偏差以及用于安装半导体器件的方法和结构。 半导体器件（5）在电极（4）上包括连接半导体器件（5）和衬底（6）的连接材料（3,9）。 连接材料包括由芯（1）和覆盖芯的导体（2）形成的复合连接材料（9），该芯在室温下的室温下的导电体的弹性模量低于室温下的低弹性模量， 和由导体形成的单层连接材料（3）。

公开(公告)号：EP1116420B1

公开(公告)日：2002-06-26

申请号：EP99952417.6

申请日：1999-08-16

Applicant: Infineon Technologies AG

Inventor： HACKE, Hans-Jürgen

IPC: H05K1/11 ,  G01R1/073 ,  G01R1/04

CPC classification number: G01R1/0735 ,  G01R31/2886 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/326 ,  H05K2201/0394 ,  H05K2201/09472

Abstract: The present invention relates to a printed circuit plate (10) which is intended for testing electric components (20) having a plurality of connection contacts (21, 22) on their surfaces. The plate comprises an electrically isolated isolation layer (11) in which through-holes (12) are formed. The area about each through-hole (12) comprises a conductive contact pad (14) located on one surface of the isolation layer (11). A printed conductor (13) extends from each contact pad (14) mainly in the direction of an edge area in the isolation layer (11).