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    SYSTEM FOR ELECTRICAL TESTING OF THROUGH-SILICON VIAS (TSVs), AND CORRESPONDING MANUFACTURING PROCESS
    2.
    发明申请
    SYSTEM FOR ELECTRICAL TESTING OF THROUGH-SILICON VIAS (TSVs), AND CORRESPONDING MANUFACTURING PROCESS 有权
    通过硅电子电气测试系统（TSV）和相应的制造工艺

    公开(公告)号：US20130256661A1

    公开(公告)日：2013-10-03

    申请号：US13855321

    申请日：2013-04-02

    Applicant: STMICROELECTRONICS S.R.I.

    Inventor： Alberto PAGANI

    IPC: H01L21/66 ,  H01L21/768

    CPC classification number: H01L22/34 ,  H01L21/743 ,  H01L21/76898 ,  H01L22/14

    Abstract: An embodiment of a process for manufacturing a system for electrical testing of a through via extending in a vertical direction through a substrate of semiconductor material envisages integrating an electrical testing circuit in the body to enable detection of at least one electrical parameter of the through via through a microelectronic buried structure defining an electrical path between electrical-connection elements towards the outside and a buried end of the through via; the integration step envisages providing a trench and forming a doped buried region at the bottom of the trench, having a doping opposite to that of the substrate so as to form a semiconductor junction, defining the electrical path when it is forward biased; in particular, the semiconductor junction has a junction area smaller than the area of a surface of the conductive region in a horizontal plane transverse to the vertical direction, in such a way as to have a reduced reverse saturation current.

    Abstract translation: 用于制造用于沿垂直方向延伸穿过半导体材料的基底的通孔的电测试的系统的实施例设想将身体中的电测试电路集成以使得能够检测穿通通孔的至少一个电参数 微电子掩埋结构，其限定朝向外部的电连接元件和通孔的埋入端之间的电路径; 集成步骤设想提供沟槽并在沟槽的底部形成掺杂的掩埋区域，其具有与衬底的掺杂相反的掺杂，以便形成半导体结，当正向偏置时限定电路径; 特别地，半导体结具有比横向于垂直方向的水平面中的导电区域的表面的面积小的结面积，使得具有减小的反向饱和电流。

    NETWORK OF ELECTRONIC DEVICES ASSEMBLED ON A FLEXIBLE SUPPORT AND COMMUNICATION METHOD
    5.
    发明申请
    NETWORK OF ELECTRONIC DEVICES ASSEMBLED ON A FLEXIBLE SUPPORT AND COMMUNICATION METHOD 有权
    电子设备网络组装在灵活的支持和通信方法上

    公开(公告)号：US20130324041A1

    公开(公告)日：2013-12-05

    申请号：US13905342

    申请日：2013-05-30

    Applicant: STMicroelectronics S.r.I.

    Inventor： Alberto PAGANI

    IPC: H04B5/00

    CPC classification number: H04B5/0075 ,  A61B5/6804 ,  A61B2562/164 ,  H01F38/14 ,  H01L23/5387 ,  H01L23/645 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01Q1/2225 ,  H01Q1/273 ,  H01Q1/526 ,  H01Q7/00 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/40 ,  H02J50/70 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0081 ,  H01L2924/00

    Abstract: An embodiment of a network of electronic devices is formed on a flexible substrate by a plurality of electronic devices assembled on the flexible substrate. The electronic devices have an embedded antenna for mutual coupling of a wireless type. Each electronic device is formed by a chip or a complex system integrating a transceiver circuit coupled to the embedded antenna and a functional part coupled to the transceiver circuit and including at least one element chosen in the group comprising: a sensor, an actuator, an interface, an electrode, a memory, a control unit, a power-supply unit, a converter, an adapter, a digital circuit, an analog circuit, an RF circuit, a microelectromechanical system, an electrode, a well, a cell, a container for liquids. The flexible support may be a substrate of plastic material that incorporates the electronic devices or a garment having smart buttons that house the electronic devices.

    Abstract translation: 通过组装在柔性基板上的多个电子装置在柔性基板上形成电子装置网络的一个实施例。 电子设备具有用于无线类型的相互耦合的嵌入式天线。 每个电子设备由芯片或复合系统形成，该系统集成耦合到嵌入式天线的收发器电路和耦合到收发器电路的功能部件，并且包括在组中选择的至少一个元件，包括：传感器，致动器，接口 ，电极，存储器，控制单元，电源单元，转换器，适配器，数字电路，模拟电路，RF电路，微机电系统，电极，阱，电池，容器 用于液体。 柔性支撑件可以是包含电子装置的塑料材料的基底或具有容纳电子装置的智能按钮的衣服。

    INTEGRATED MICRO-ELECTROMECHANICAL DEVICE OF SEMICONDUCTOR MATERIAL HAVING A DIAPHRAGM, SUCH AS A PRESSURE SENSOR AND AN ACTUATOR
    6.
    发明申请
    INTEGRATED MICRO-ELECTROMECHANICAL DEVICE OF SEMICONDUCTOR MATERIAL HAVING A DIAPHRAGM, SUCH AS A PRESSURE SENSOR AND AN ACTUATOR 审中-公开
    具有膜片的半导体材料的集成微电气装置，例如压力传感器和执行器

    公开(公告)号：US20160176702A1

    公开(公告)日：2016-06-23

    申请号：US14856707

    申请日：2015-09-17

    Applicant: STMICROELECTRONICS S.r.I.

    Inventor： Alberto PAGANI ,  Alessandro MOTTA

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B7/0074 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0116 ,  G01L9/0045

    Abstract: An integrated micro-electromechanical device includes a first body of semiconductor material having a first face and a second face opposite the first surface, with the first body including a buried cavity forming a diaphragm delimited between the buried cavity and the first face. The diaphragm is monolithic with the first body. At least one first magnetic via extends between the second face and the buried cavity of the first body. A first magnetic region extends over the first face of the first body. A first coil extends over the second face of the first body and is magnetically coupled to the first magnetic via.

    Abstract translation: 集成的微机电装置包括具有第一面和与第一表面相对的第二面的半导体材料的第一本体，第一主体包括形成在掩埋腔和第一面之间的隔膜的掩埋腔。 隔膜与第一个主体是整体的。 至少一个第一磁通孔在第二面和第一主体的埋入腔之间延伸。 第一磁性区域在第一主体的第一面上延伸。 第一线圈在第一主体的第二面上延伸并且磁耦合到第一磁通孔。

    INTEGRATED CIRCUIT (IC) INCLUDING SEMICONDUCTOR RESISTOR AND RESISTANCE COMPENSATION CIRCUIT AND RELATED METHODS
    7.
    发明申请
    INTEGRATED CIRCUIT (IC) INCLUDING SEMICONDUCTOR RESISTOR AND RESISTANCE COMPENSATION CIRCUIT AND RELATED METHODS 有权
    包含半导体电阻和电阻补偿电路的集成电路（IC）及相关方法

    公开(公告)号：US20170005043A1

    公开(公告)日：2017-01-05

    申请号：US14754799

    申请日：2015-06-30

    Applicant: STMICROELECTRONICS S.r.I.

    Inventor： Alberto PAGANI ,  Alessandro Motta

    IPC: H01L23/00 ,  H01C7/10 ,  H01L23/34 ,  H01L29/36 ,  H01L27/02 ,  H01L49/02

    CPC classification number: H01C7/10 ,  H01L22/34 ,  H01L23/34 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/36

    Abstract: An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the semiconductor substrate and having a first conductivity type, a first resistive region in the well having an L-shape and a second conductivity type, and a tuning element associated with the first resistive region. The IC may also include a resistance compensation circuit on the semiconductor substrate. The resistance compensation circuit may be configured to measure an initial resistance of the first resistive region, and generate a voltage at the tuning element to tune an operating resistance of the first resistive region based upon the measured initial resistance.

    Abstract translation: 集成电路（IC）可以包括半导体衬底和半导体电阻器。 半导体电阻器可以包括在半导体衬底中并且具有第一导电类型的阱，阱中的第一电阻区域具有L形和第二导电类型，以及与第一电阻区域相关联的调谐元件。 IC还可以包括在半导体衬底上的电阻补偿电路。 电阻补偿电路可以被配置为测量第一电阻区域的初始电阻，并且在调谐元件处产生电压，以基于测量的初始电阻来调节第一电阻区域的工作电阻。

    PROCESS FOR CONTROLLING THE CORRECT POSITIONING OF TEST PROBES ON TERMINATIONS OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR AND CORRESPONDING ELECTRONIC DEVICE
    8.
    发明申请
    PROCESS FOR CONTROLLING THE CORRECT POSITIONING OF TEST PROBES ON TERMINATIONS OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR AND CORRESPONDING ELECTRONIC DEVICE 审中-公开
    用于控制集成在半导体和相应电子器件上的电子器件终止的测试探针的正确定位的过程

    公开(公告)号：US20160018461A1

    公开(公告)日：2016-01-21

    申请号：US14868904

    申请日：2015-09-29

    Applicant: STMicroelectronics S.r.I.

    Inventor： Alberto PAGANI

    IPC: G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/2889 ,  G01R31/2891

    Abstract: An electrical check executed on wafer tests for the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on the wafer. A signal is applied to cause a current to circulate in at least part of a seal ring of at least one of the electronic devices. In a case where the current flows between and through multiple electronic devices, the seal rings of those electronic devices are suitably interconnected to each other by electronic structures that extend through the scribe line between electronic devices.

    Abstract translation: 在晶片测试上进行电检查，以正确地定位或对准探针卡的探针在集成在晶片上的电子设备的焊盘或凸块上。 施加信号以使电流在至少一个电子设备的密封环的至少一部分中循环。 在电流在多个电子设备之间流动的情况下，这些电子设备的密封环通过在电子设备之间延伸穿过划线的电子结构彼此适当地互连。

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