公开(公告)号：US09502620B2

公开(公告)日：2016-11-22

申请号：US14988537

申请日：2016-01-05

Applicant: Xenio Corporation

Inventor： Brian Cumpston

IPC: H01L27/15 ,  H01L29/88 ,  H01L33/48 ,  H01L33/62 ,  H01L33/60 ,  H01L25/16 ,  H05K1/18 ,  H05K1/02 ,  H01L33/58 ,  H01L33/20 ,  H01L33/50 ,  H01L33/56 ,  H01L33/64 ,  H01L25/075

CPC classification number: H01L33/486 ,  H01L25/0753 ,  H01L25/165 ,  H01L25/167 ,  H01L33/20 ,  H01L33/507 ,  H01L33/56 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L33/644 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/181 ,  H05K1/0274 ,  H05K1/184 ,  H05K2201/10106 ,  H05K2201/10643 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A low-cost device for packaging LED dies provides superior reflectivity and thermal conductivity without covering entire surfaces of an LED luminaire with an expensive reflective aluminum substrate. The LED packaging device includes a highly reflective substrate disposed in a hole in a printed circuit board. The substrate has a reflectivity greater than 97% and includes an insulating layer and a reflective layer disposed above a thicker aluminum layer. An LED die is disposed on the top surface of the substrate. The PCB has a layer of glass fiber in resin and a metal layer. The lower surface of the PCB and the bottom surface of the substrate are substantially coplanar. The metal layer of the PCB is electrically coupled to the LED die only through bond wires. Electronic circuitry is disposed on the upper surface of the PCB and is used to control light emitted from the LED die.

公开(公告)号：US09095067B2

公开(公告)日：2015-07-28

申请号：US14069054

申请日：2013-10-31

Applicant: Wintec Industries, Inc.

Inventor： Kong-Chen Chen

IPC: H05K1/11 ,  H05K3/30 ,  H01L23/64 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/64 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/181 ,  H05K3/301 ,  H05K3/341 ,  H05K2201/086 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y02P70/611 ,  Y10T29/4902 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: An electronic device is presented for electrical connection between a first pad contact of an integrated circuit component and a target contact positioned substantially in a first plane of a target platform. The electronic device includes a first surface substantially parallel to the first plane and a second surface below the first surface substantially parallel to the first plane. The first surface includes a first contact region configured to connect to the first pad contact when the electronic device is connected between the first pad contact and the target contact. The second surface includes a second contact region configured to connect to the target contact when the electronic device is connected between the first pad contact and the target contact. The electronic device further includes a multitude of electrically passive elements connected between the first and second contact regions.

Abstract translation: 呈现电子设备用于集成电路部件的第一焊盘触点和基本上位于目标平台的第一平面中的目标触点之间的电连接。 电子设备包括基本上平行于第一平面的第一表面和基本上平行于第一平面的第一表面下方的第二表面。 第一表面包括第一接触区域，被配置为当电子设备连接在第一焊盘触点和目标触点之间时连接到第一焊盘触点。 第二表面包括被配置为当电子设备连接在第一焊盘触点和目标触点之间时连接到目标触点的第二触点区域。 电子设备还包括连接在第一和第二接触区域之间的多个电动无源元件。

公开(公告)号：US08319334B2

公开(公告)日：2012-11-27

申请号：US12538470

申请日：2009-08-10

Applicant: Martin Standing

Inventor： Martin Standing

IPC: H01L23/12 ,  H01L21/00

CPC classification number: H05K1/185 ,  H01L21/4846 ,  H01L23/3107 ,  H01L23/5389 ,  H01L25/072 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2201/10643 ,  H01L2924/00

Abstract: An electronic device includes at least one semiconductor chip, each semiconductor chip defining a first main face and a second main face opposite to the first main face. A first metal layer is coupled to the first main face of the at least one semiconductor chip and a second metal layer is coupled to the second main face of the at least one semiconductor chip. A third metal layer overlies the first metal layer and a fourth metal layer overlies the second metal layer. A first through-connection extends from the third metal layer to the fourth metal layer, the first through-connection being electrically connected with the first metal layer and electrically disconnected from the second metal layer. A second through-connection extends from the third metal layer to the fourth metal layer, the second through-connection being electrically connected with the second metal layer and electrically disconnected from the first metal layer.

Abstract translation: 电子设备包括至少一个半导体芯片，每个半导体芯片限定第一主面和与第一主面相对的第二主面。 第一金属层耦合到至少一个半导体芯片的第一主面，第二金属层耦合到至少一个半导体芯片的第二主面。 第三金属层覆盖在第一金属层上，第四金属层覆盖在第二金属层上。 第一贯通连接从第三金属层延伸到第四金属层，第一贯通连接与第一金属层电连接并与第二金属层电连接。 第二贯通连接从第三金属层延伸到第四金属层，第二贯通连接与第二金属层电连接并与第一金属层电连接。

公开(公告)号：US08279616B2

公开(公告)日：2012-10-02

申请号：US13064541

申请日：2011-03-30

Applicant: Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

Inventor： Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/0236 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A printed circuit board having an embedded chip capacitor includes a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, having a first electrode connected to the first conductive layer through being seated in a cavity formed between the first conductive layer and the second conductive layer; a filled material, filled in a space excluding a space occupied by the chip capacitor in the cavity; and a via, penetrating the filled material and connecting the second conductive layer to the second electrode of the chip capacitor.

Abstract translation: 具有嵌入式芯片电容器的印刷电路板包括：第一导电层; 远离所述第一导电层放置的第二导电层; 芯片电容器，其具有通过位于形成在第一导电层和第二导电层之间的空腔中而连接到第一导电层的第一电极; 填充材料，填充在空腔内不包括由片状电容器占据的空间的空间中; 以及通孔，穿透填充材料并将第二导电层连接到片式电容器的第二电极。

公开(公告)号：US08116066B2

公开(公告)日：2012-02-14

申请号：US12366140

申请日：2009-02-05

Applicant: Osamu Inoue

Inventor： Osamu Inoue

IPC: H01G4/06

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/061 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2203/1152 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component.

Abstract translation: 在本发明的电子部件内置基板的制造方法中，具有第一绝缘层，形成在对应于部件安装区域的部分的第一绝缘层下方的止动金属层的安装体和第二绝缘层 形成在第一绝缘层的下表面上并覆盖止动金属层，并且通过对与元件安装区域相对应的第一绝缘层的一部分进行穿透处理而形成凹部以形成开口部， 同时使用塞子金属层作为塞子。 此外，去除凹部中的止动金属层，然后将电子部件安装在凹部上，然后在电子部件上形成第三绝缘层。

公开(公告)号：US20110085311A1

公开(公告)日：2011-04-14

申请号：US12631649

申请日：2009-12-04

Applicant: Kong-Chen Chen

Inventor： Kong-Chen Chen

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H05K1/111 ,  H01L23/64 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/181 ,  H05K3/301 ,  H05K3/341 ,  H05K2201/086 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y02P70/611 ,  Y10T29/4902 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Electrically passive components are constructed in a structure that is substantially perpendicular to target platform including a first plane to provide a larger electrode contact area and a smaller physical dimension. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.

Abstract translation: 公开了用于构造垂直配置的无源电子部件的制造技术。 电动无源部件构造成基本上垂直于包括第一平面的靶平台的结构，以提供更大的电极接触面积和更小的物理尺寸。 被构造为基本上垂直于与目标平台相关的平面的被动部件可以直接连接到集成电路或基板的焊盘触点，或者可以嵌入封装中以减少被动部件的面积开销，同时提高 被动元件在其应用中。

公开(公告)号：US07791896B1

公开(公告)日：2010-09-07

申请号：US11820570

申请日：2007-06-20

Applicant: Jun Fan ,  James L. Knighten ,  Norman W. Smith

Inventor： Jun Fan ,  James L. Knighten ,  Norman W. Smith

IPC: H05K1/16

CPC classification number: H05K1/0231 ,  H05K1/185 ,  H05K2201/09309 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A circuit board includes power reference layers and a capacitor provided between the power reference layers such that a shorter dimension of the capacitor defines a space between the power reference layers. The capacitor has plural conductive plates and plural dielectric layers.

Abstract translation: 电路板包括功率参考层和设置在功率参考层之间的电容器，使得电容器的较短尺寸限定功率参考层之间的空间。 电容器具有多个导电板和多个电介质层。

公开(公告)号：US20100027228A1

公开(公告)日：2010-02-04

申请号：US12510028

申请日：2009-07-27

Applicant: Kiyotaka TSUKADA ,  Toshihiro NOMURA ,  Daisuke MINOURA

Inventor： Kiyotaka TSUKADA ,  Toshihiro NOMURA ,  Daisuke MINOURA

IPC: H01R9/00 ,  H05K3/30

CPC classification number: H05K1/145 ,  H01L24/01 ,  H01L24/25 ,  H01L2224/2518 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/0204 ,  H05K3/284 ,  H05K3/306 ,  H05K2201/096 ,  H05K2201/10166 ,  H05K2201/10303 ,  H05K2201/10424 ,  H05K2201/10643 ,  H05K2201/10871 ,  H05K2201/10946 ,  Y10T29/4913 ,  Y10T29/49153 ,  H01L2924/00

Abstract: A semiconductor device includes wiring boards each having an insulating board, conductor circuits and through-holes, the insulating board having top and bottom surfaces, the conductor circuits formed on the top and bottom surfaces, the through holes penetrating the insulating board and electrically connecting the conductor circuits of the top and bottom surfaces; conductor posts each having flange, head and leg portions, the flange portion having first and second surfaces and having an external diameter larger than that of the through-hole, the head portion protruding from the first surface, the leg portion protruding from the second surface; and electronic components each having an electrode formed on one or more surfaces and connected to the leg portion. The head portion is inserted until the first surface of the flange portion comes into contact with the bottom surface of the wiring board and electrically connected at an inner wall of the through-hole.

Abstract translation: 半导体器件包括各自具有绝缘板，导体电路和通孔的布线板，所述绝缘板具有顶表面和底表面，所述导体电路形成在顶表面和底表面上，所述通孔穿过绝缘板并电连接 顶表面和底表面的导体电路; 导体柱各自具有凸缘，头部和腿部，凸缘部分具有第一和第二表面，并且具有比通孔大的外径，头部从第一表面突出，腿部从第二表面突出 ; 以及各自具有形成在一个或多个表面上并连接到所述腿部的电极的电子部件。 插入头部直到凸缘部分的第一表面与布线板的底表面接触并且在通孔的内壁处电连接。

公开(公告)号：US07625666B2

公开(公告)日：2009-12-01

申请号：US11905282

申请日：2007-09-28

Applicant: Tomoyuki Shose ,  Katsuyuki Kida ,  Masao Kondou ,  Yasuo Akai

Inventor： Tomoyuki Shose ,  Katsuyuki Kida ,  Masao Kondou ,  Yasuo Akai

IPC: H01M2/02

CPC classification number: H01M2/0413 ,  H01M2/0222 ,  H01M10/052 ,  H05K3/341 ,  H05K2201/0373 ,  H05K2201/10462 ,  H05K2201/10643 ,  H05K2201/10659 ,  Y02P70/613 ,  Y10S228/901

Abstract: A lead plate-attached coin-type battery is constituted from a combination of a coin-type battery and a positive lead plate. In the coin-type battery, a negative cap seals the aperture of a positive outer can. In a lateral view, the positive lead plate is crank-shaped, and one end thereof is attached to the outer surface of the positive outer can of the coin-type battery. A lead plate is not attached to the negative cap. One or more projections that project in the Z axis direction are provided on the negative cap. In the lead plate-attached coin-type battery, the positive lead plate and negative cap have been attached to respective conductive lands on a circuit board by a solder reflow method.

Abstract translation: 引线板式硬币型电池由硬币型电池和正极引线板的组合构成。 在硬币型电池中，负极帽密封正外壳的孔径。 在侧视图中，正极引线板是曲柄形的，其一端连接到硬币型电池的正外壳的外表面。 引线板未连接到负极盖。 在Z轴方向上投影的一个或多个突起设置在负极盖上。 在带引线板的硬币型电池中，通过焊料回流法将正极引线板和负极盖安装在电路板上的各个导电焊盘上。

公开(公告)号：US07196909B2

公开(公告)日：2007-03-27

申请号：US10771166

申请日：2004-02-04

Applicant: Tomokazu Katsuyama

Inventor： Tomokazu Katsuyama

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H01P1/047 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2223/665 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01P1/2007 ,  H05K1/0219 ,  H05K1/0231 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This invention is directed to reduce degradation, loss, and reflection of high frequency signals of a coupling circuit for an alternating current. The coupling circuit, for connecting a first circuit element to a second circuit element, comprises a die capacitor and a chip capacitor connected in parallel to each other. The die capacitor has a first electrode that faces to and is in contact with the first circuit element, and a second electrode that is wire-bonded to the second circuit element. The chip capacitor also has a first electrode that is in contact with the first circuit element and a second electrode that is in contact with the second electrode of the die capacitor. The coupling circuit may show both advantages of superior performance at high frequencies attributed to the die-capacitor and relative large capacitance attributed to the chip-capacitor.

Abstract translation: 本发明旨在减少交流电耦合电路的高频信号的劣化，损耗和反射。 用于将第一电路元件连接到第二电路元件的耦合电路包括彼此并联连接的管芯电容器和片式电容器。 管芯电容器具有面向第一电极并与第一电路元件接触的第一电极，以及与第二电路元件引线接合的第二电极。 芯片电容器还具有与第一电路元件接触的第一电极和与模具电容器的第二电极接触的第二电极。 耦合电路可以显示归因于芯片电容器的高频下的优异性能和归因于芯片电容器的相对大的电容的两个优点。