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786 条记录 (耗时 0.037 秒)

    Method of selectively forming a silicon nitride layer
    92.
    发明授权
    Method of selectively forming a silicon nitride layer 有权
    选择性地形成氮化硅层的方法

    公开(公告)号：US08334220B2

    公开(公告)日：2012-12-18

    申请号：US11689325

    申请日：2007-03-21

    申请人： Chen-Hua Yu

    发明人： Chen-Hua Yu

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/02354 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/3185 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

    摘要： A method for selectively forming a dielectric layer. An embodiment includes forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This method allows for a protective silicon nitride layer to be formed, while also preventing and/or reducing the nitrogen itself from penetrating far enough to contaminate the substrate. In another embodiment the treating with nitrogen is continued to form not only a silicon nitride, but to also diffuse a small portion of nitrogen into the dielectric layer to nitridized a portion of the dielectric layer. Optionally, an anneal could be performed to repair any damage that has been done by the treatment process.

    摘要翻译： 一种选择性地形成电介质层的方法。 实施例包括在半导体衬底上形成诸如氧化物层的电介质层，在电介质层上沉积硅层，并用氮处理硅层，从而将硅层转化为氮化硅层。 该方法允许形成保护性氮化硅层，同时还防止和/或减少氮本身渗透到足以污染衬底。 在另一个实施方案中，氮的处理继续不仅形成氮化硅，而且还将少部分氮扩散到电介质层中以将电介质层的一部分氮化。 任选地，可以进行退火以修复由处理过程进行的任何损坏。

    High-k gate dielectric and method of manufacture
    94.
    发明授权
    High-k gate dielectric and method of manufacture 有权
    高k栅介质及其制造方法

    公开(公告)号：US08294201B2

    公开(公告)日：2012-10-23

    申请号：US13209493

    申请日：2011-08-15

    申请人： Chen-Hua Yu ,  Liang-Gi Yao

    发明人： Chen-Hua Yu ,  Liang-Gi Yao

    IPC分类号： H01L29/792

    CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

    摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

    摘要翻译： 为高k栅极电介质和栅电极提供了一种器件和形成方法。 形成高k电介质材料，并且在高k电介质材料上形成富硅膜。 然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间​​的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。 然后通过受控的工艺在膜上形成导电材料以产生栅极导体。

    N-FET with a highly doped source/drain and strain booster
    96.
    发明授权
    N-FET with a highly doped source/drain and strain booster 有权
    具有高掺杂源/漏极和应变增强器的N-FET

    公开(公告)号：US08247285B2

    公开(公告)日：2012-08-21

    申请号：US12341674

    申请日：2008-12-22

    申请人： Jing-Cheng Lin ,  Chen-Hua Yu

    发明人： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7848 ,  H01L21/26586 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/7833

    摘要： A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1-xGex source/drain regions are doped in-situ during formation, x

    摘要翻译： 提出了制造具有高掺杂源/漏和应变增强器的N-FET的结构和方法。 该方法提供具有Ge沟道区的衬底。 在Ge沟道上方形成栅极电介质，在栅极电介质上形成栅电极。 牺牲栅间隔件设置在栅极电介质和栅电极的侧壁上。 凹坑被蚀刻到在牺牲栅极间隔物下面延伸的衬底中。 Si1-xGex源/漏区在形成期间原位掺杂，x <0.85。

    Method of separating light-emitting diode from a growth substrate
    97.
    发明授权
    Method of separating light-emitting diode from a growth substrate 有权
    从生长衬底分离发光二极管的方法

    公开(公告)号：US08236583B2

    公开(公告)日：2012-08-07

    申请号：US12554578

    申请日：2009-09-04

    申请人： Ding-Yuan Chen ,  Hung-Ta Lin ,  Chen-Hua Yu ,  Wen-Chih Chiou

    发明人： Ding-Yuan Chen ,  Hung-Ta Lin ,  Chen-Hua Yu ,  Wen-Chih Chiou

    IPC分类号： H01L21/00

    CPC分类号： H01L33/007 ,  C23C14/048 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L25/167 ,  H01L33/0079 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a light-emitting diode (LED) device and separating the LED device from a growth substrate is provided. The LED device is formed by forming an LED structure over a growth substrate. The method includes forming and patterning a mask layer on the growth substrate. A first contact layer is formed over the patterned mask layer with an air bridge between the first contact layer and the patterned mask layer. The first contact layer may be a contact layer of the LED structure. After the formation of the LED structure, the growth substrate is detached from the LED structure along the air bridge.

    摘要翻译： 提供一种形成发光二极管（LED）器件并将LED器件与生长衬底分离的方法。 LED器件通过在生长衬底上形成LED结构而形成。 该方法包括在生长衬底上形成和图案化掩模层。 在图案化掩模层上形成第一接触层，在第一接触层和图案化掩模层之间具有空气桥。 第一接触层可以是LED结构的接触层。 在形成LED结构之后，生长衬底沿着空气桥与LED结构分离。

    Schemes for forming barrier layers for copper in interconnect structures
    98.
    发明授权
    Schemes for forming barrier layers for copper in interconnect structures 有权
    用于在互连结构中形成铜的阻挡层的方案

    公开(公告)号：US08232201B2

    公开(公告)日：2012-07-31

    申请号：US13115161

    申请日：2011-05-25

    申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

    IPC分类号： H01L21/44

    CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

    摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

    Process for Improving Copper Line Cap Formation
    99.
    发明申请
    Process for Improving Copper Line Cap Formation 有权
    改善铜线帽形成的工艺

    公开(公告)号：US20120190191A1

    公开(公告)日：2012-07-26

    申请号：US13440704

    申请日：2012-04-05

    申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

    摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

    摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。