公开(公告)号：US20100213511A1

公开(公告)日：2010-08-26

申请号：US12773735

申请日：2010-05-04

Applicant: Anthony J. Lochtefeld

Inventor： Anthony J. Lochtefeld

IPC: H01L29/04

CPC classification number: H01L21/02488 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/2018 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795

Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.

Abstract translation: 具有在侧壁结构内捕获缺陷的构型的晶格不匹配材料。

公开(公告)号：US20100207138A1

公开(公告)日：2010-08-19

申请号：US12767783

申请日：2010-04-26

Applicant: Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

Inventor： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

IPC: H01L33/30 ,  H01L29/20

CPC classification number: H01L33/007 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02645 ,  H01L33/0075 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 μm or more but 600 μm or less in thickness, and is 0.2 mm or more but 50 mm or less in width.

Abstract translation: 尺寸适合于半导体器件的III族氮化物半导体晶体及其制造方法，III族氮化物半导体器件及其制造方法以及发光器具。 制造III族氮化物半导体晶体的方法包括在起始衬底上生长至少一种III族氮化物半导体晶体衬底的工艺，在III族氮化物半导体晶体衬底上生长至少一种III族氮化物半导体晶体层的工艺 以及从起始基板分离由III族氮化物半导体晶体基板和III族氮化物半导体晶体层构成的III族氮化物半导体晶体的工序，其特征在于，所述III族氮化物半导体晶体为10μm 以上且600μm以下，宽度为0.2mm以上且50mm以下。

公开(公告)号：US07749905B2

公开(公告)日：2010-07-06

申请号：US12167686

申请日：2008-07-03

Applicant: Guy M. Cohen ,  Paul M. Solomon

Inventor： Guy M. Cohen ,  Paul M. Solomon

IPC: H01L21/44

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828 ,  Y10S977/762 ,  Y10S977/938

Abstract: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

Abstract translation: 公开了一种具有形成FET沟道的纳米线的垂直FET结构。 纳米线形成在导电硅化物层上。 纳米线由周围的门浇口。 顶部和底部绝缘体插塞用作栅极间隔，并减少栅极 - 源极和栅极 - 漏极电容。

公开(公告)号：US20100148221A1

公开(公告)日：2010-06-17

申请号：US12633313

申请日：2009-12-08

Applicant: Young-June Yu ,  Munib Wober ,  Thomas P.H.F. Wendling

Inventor： Young-June Yu ,  Munib Wober ,  Thomas P.H.F. Wendling

IPC: H01L31/105 ,  H01L31/18

CPC classification number: H01L21/0237 ,  B82Y20/00 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L31/035227

Abstract: An embodiment relates to a device comprising a nanowire photodiode comprising a nanowire and at least on vertical photogate operably coupled to the nanowire photodiode.

Abstract translation: 实施例涉及包括纳米线光电二极管的器件，该纳米线光电二极管包括可操作地耦合到纳米线光电二极管的纳米线和至少在垂直光栅上。

公开(公告)号：US20100144126A1

公开(公告)日：2010-06-10

申请号：US12708007

申请日：2010-02-18

Applicant: Eun Kyung LEE ,  Byoung Lyong CHOI ,  Young KUK ,  Je Hyuk CHOI ,  Hun Huy JUNG

Inventor： Eun Kyung LEE ,  Byoung Lyong CHOI ,  Young KUK ,  Je Hyuk CHOI ,  Hun Huy JUNG

IPC: H01L21/203

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/02568 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/0673 ,  H01L31/035281 ,  H01L33/08 ,  H01L33/20 ,  Y10S977/70 ,  Y10S977/762 ,  Y10S977/84

Abstract: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.

Abstract translation: 提供了水平纳米线场地选择性生长的方法。 根据该方法，具有预定长度和直径的水平纳米线可以在平行于基板的方向上在所需位置选择性地生长，从而制造具有高集成度的装置。 还提供了通过包括纳米线的方法和纳米器件生长的纳米线。

公开(公告)号：US20100108132A1

公开(公告)日：2010-05-06

申请号：US12261171

申请日：2008-10-30

Applicant: Loucas Tsakalakos ,  Bastiaan Arie Korevaar ,  Joleyn Eileen Balch ,  Jody Fronheiser ,  Bo Li ,  Anis Zribi

Inventor： Loucas Tsakalakos ,  Bastiaan Arie Korevaar ,  Joleyn Eileen Balch ,  Jody Fronheiser ,  Bo Li ,  Anis Zribi

IPC: H01L31/0352 ,  H01L21/20 ,  H01L29/06

CPC classification number: H01L21/02381 ,  B81B1/00 ,  B81B2201/0214 ,  B81B2201/0292 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L31/035227 ,  H01L31/03529

Abstract: Disclosed herein is a nanodevice. Disclosed herein too is a method of manufacturing a nanodevice. In one embodiment the nanodevice includes a first substrate; a second substrate; a nanowire; the nanowire contacting the first substrate and the second substrate; the nanowire comprising a metal, a semi-conductor or a combination thereof.

Abstract translation: 本文公开了一种纳米器件。 这里也公开了一种制造纳米器件的方法。 在一个实施例中，纳米器件包括第一衬底; 第二基板; 纳米线 所述纳米线与所述第一基板和所述第二基板接触; 纳米线包括金属，半导体或其组合。

公开(公告)号：US20100096614A1

公开(公告)日：2010-04-22

申请号：US12385744

申请日：2009-04-17

Applicant: Junyoun Kim ,  Taek Kim ,  Kyoungkook Kim

Inventor： Junyoun Kim ,  Taek Kim ,  Kyoungkook Kim

IPC: H01L33/00

CPC classification number: H01L33/08 ,  H01L21/0237 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0259 ,  H01L21/02645 ,  H01L21/02653 ,  H01L33/0079

Abstract: A light-emitting diode and a method of manufacturing the light-emitting diode are provide, the light-emitting diode including a lower electrode on a substrate, a template layer on the lower electrode. The template layer may have a plurality of open regions. A plurality of nano-dashes may be formed in the plurality of open regions of the template layer. A transparent insulating layer may be formed between the nano-dashes. A transparent upper electrode may be formed on the nano-dashes and the transparent insulating layer.

Abstract translation: 提供发光二极管和制造发光二极管的方法，发光二极管包括在基底上的下电极，下电极上的模板层。 模板层可以具有多个开放区域。 可以在模板层的多个开放区域中形成多个纳米短边。 可以在纳米短边之间形成透明绝缘层。 透明上电极可以形成在纳米薄片和透明绝缘层上。

公开(公告)号：US07696097B2

公开(公告)日：2010-04-13

申请号：US12051513

申请日：2008-03-19

Applicant: Eun Kyung Lee ,  Byoung Lyong Choi ,  Young Kuk ,  Je Hyuk Choi ,  Hun Huy Jung

Inventor： Eun Kyung Lee ,  Byoung Lyong Choi ,  Young Kuk ,  Je Hyuk Choi ,  Hun Huy Jung

IPC: H01L29/06 ,  H01L21/311

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/02568 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/0673 ,  H01L31/035281 ,  H01L33/08 ,  H01L33/20 ,  Y10S977/70 ,  Y10S977/762 ,  Y10S977/84

Abstract: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.

Abstract translation: 提供了水平纳米线场地选择性生长的方法。 根据该方法，具有预定长度和直径的水平纳米线可以在平行于基板的方向上在所需位置选择性地生长，从而制造具有高集成度的装置。 还提供了通过包括纳米线的方法和纳米器件生长的纳米线。

公开(公告)号：US20100075469A1

公开(公告)日：2010-03-25

申请号：US12384331

申请日：2009-04-02

Applicant: Kai Liu ,  Kai-Li Jiang ,  Shou-Shan Fan

Inventor： Kai Liu ,  Kai-Li Jiang ,  Shou-Shan Fan

IPC: H01L21/336

CPC classification number: H01L51/0541 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02527 ,  H01L21/02645 ,  H01L21/02664 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0002 ,  H01L51/0013 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/708 ,  Y10S977/72 ,  Y10S977/723 ,  Y10S977/742 ,  Y10S977/743 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/779 ,  Y10S977/784 ,  Y10S977/789 ,  Y10S977/796

Abstract: A method for making a thin film transistor, the method comprising the steps of: (a) providing a carbon nanotube array and an insulating substrate; (b) pulling out a carbon nanotube film from the carbon nanotube array by using a tool; (c) placing at least one carbon nanotube film on a surface of the insulating substrate, to form a carbon nanotube layer thereon; (d) forming a source electrode and a drain electrode; wherein the source electrode and the drain electrode being spaced therebetween, and electrically connected to the carbon nanotube layer; and (e) covering the carbon nanotube layer with an insulating layer, and a gate electrode being located on the insulating layer.

Abstract translation: 一种制造薄膜晶体管的方法，所述方法包括以下步骤：（a）提供碳纳米管阵列和绝缘基板; （b）使用工具从碳纳米管阵列拉出碳纳米管膜; （c）在绝缘基板的表面上放置至少一个碳纳米管膜，在其上形成碳纳米管层; （d）形成源电极和漏电极; 其中所述源电极和所述漏极彼此间隔开并且电连接到所述碳纳米管层; 和（e）用绝缘层覆盖碳纳米管层，并且栅电极位于绝缘层上。

公开(公告)号：US07666708B2

公开(公告)日：2010-02-23

申请号：US11543352

申请日：2006-10-04

Applicant: Charles M. Lieber ,  Yi Cui ,  Xiangfeng Duan ,  Yu Huang

Inventor： Charles M. Lieber ,  Yi Cui ,  Xiangfeng Duan ,  Yu Huang

IPC: H01L51/40 ,  D01C5/00 ,  D01F9/12

CPC classification number: H01L29/0665 ,  B01J23/50 ,  B01J23/52 ,  B01J23/72 ,  B01J35/0013 ,  B01J37/349 ,  B81C1/0019 ,  B81C1/00206 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  C30B11/00 ,  C30B25/005 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/025 ,  G11C13/04 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02573 ,  H01L21/02581 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/1602 ,  H01L29/18 ,  H01L29/20 ,  H01L29/207 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/267 ,  H01L33/06 ,  H01L33/18 ,  H01L33/20 ,  H01L51/002 ,  H01L51/0048 ,  H01L2924/0002 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S438/962 ,  Y10S977/762 ,  Y10S977/847 ,  Y10S977/858 ,  Y10S977/882 ,  Y10S977/883 ,  Y10S977/892 ,  Y10S977/936 ,  Y10T428/24 ,  H01L2924/00

Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal is, axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less an 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety assembling techniques may be used to fabricate devices from such a semiconductor.

Abstract translation: 一种体积掺杂半导体，其为以下至少一种：单晶，细长体和体掺杂半导体，其沿​​着其纵向的任何点为轴线，具有小于500纳米的最大横截面尺寸，以及 具有至少一个具有小于500纳米的最小宽度的部分的独立且体积掺杂的半导体。 这种半导体的至少一部分可以具有小于200纳米，或小于150纳米，或小于100纳米，或小于80纳米，或小于70纳米，或小于60纳米或更小的最小宽度 小于20纳米，或小于10纳米，或甚至更小的5纳米。 这样的半导体可以在生长期间被掺杂。 这样的半导体可以是设备的一部分，其可以包括各种设备及其组合中的任何一种，并且可以使用各种组合技术来从这样的半导体制造设备。