公开(公告)号：US06941649B2

公开(公告)日：2005-09-13

申请号：US10068745

申请日：2002-02-05

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US20050167811A1

公开(公告)日：2005-08-04

申请号：US10906152

申请日：2005-02-04

Applicant: Roland Frech ,  Bernd Garben ,  Erich Klink ,  Stefano Oggioni

Inventor： Roland Frech ,  Bernd Garben ,  Erich Klink ,  Stefano Oggioni

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H01L23/495

CPC classification number: H05K1/0216 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/09327 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.

Abstract translation: 用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。 导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。 通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

公开(公告)号：US06750403B2

公开(公告)日：2004-06-15

申请号：US10125246

申请日：2002-04-18

Applicant: Melvin Peterson

Inventor： Melvin Peterson

IPC: H05K103

CPC classification number: H05K1/0218 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/0005 ,  H05K2201/0723 ,  H05K2201/09327 ,  H01L2924/00

Abstract: The present invention is a reconfigurable substrate which includes at least one signal line layer stack. Each signal line layer stack is defined to include two substantially parallel insulating layers and a signal line layer interposed between the two insulating layers and substantially parallel to the insulating layers. The substrate includes at least one conductive isolation layer adjacent to at least one signal line layer stack and substantially parallel to the at least one signal line layer stack. The substrate is reconfigurable to different performance levels by adding or removing at least one conductive isolation layer.

Abstract translation: 本发明是一种可重构衬底，其包括至少一个信号线层堆叠。 每个信号线层堆叠被限定为包括两个基本上平行的绝缘层和插入在两个绝缘层之间并且基本上平行于绝缘层的信号线层。 衬底包括与至少一个信号线层堆叠相邻并且基本上平行于至少一个信号线层堆叠的至少一个导电隔离层。 通过添加或去除至少一个导电隔离层，衬底可重新配置成不同的性能水平。

公开(公告)号：US06477060B1

公开(公告)日：2002-11-05

申请号：US09608907

申请日：2000-06-30

Applicant: Erik W. Peter ,  Jeffrey M. Shuey ,  Ronald Martin

Inventor： Erik W. Peter ,  Jeffrey M. Shuey ,  Ronald Martin

IPC: H05K114

CPC classification number: H05K1/0237 ,  H05K1/0298 ,  H05K2201/044 ,  H05K2201/09327

Abstract: A printed circuit board utilizes asymmetric striplines to accommodate a large number of transmission lines on a six-layer board. The asymmetric striplines are formed from two signal layers that are sandwiched between two reference planes such that the traces in each signal layer form asymmetric striplines with the two reference planes. Two additional signal layers are arranged on the outside of the reference planes so as to form microstrips with the reference planes.

Abstract translation: 印刷电路板利用不对称带状线在六层板上容纳大量传输线。 不对称带状线由夹在两个参考平面之间的两个信号层形成，使得每个信号层中的迹线与两个参考平面形成不对称的带状线。 两个额外的信号层布置在参考平面的外侧，以便与参考平面形成微带。

公开(公告)号：US20020153613A1

公开(公告)日：2002-10-24

申请号：US09800409

申请日：2001-03-06

Applicant: Mitac International Corp.

Inventor： Yu-Chiang Cheng

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327 ,  Y10T29/49126

Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.0 mm. Each of the first and fifth insulating substrates has a thickness ranging from 5.225 to 5.775 mil. Each of the second and fourth insulating substrates has a thickness ranging from 7.6 to 8.4 mil. The third insulating substrate has a thickness ranging from 3.8 to 4.2 mil. The first signal wiring layer has a first resistance with respect to the ground wiring layer. The second signal wiring layer has a second resistance with respect to the ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the power wiring layer. The first, second, third and fourth resistances are within the range of 49.5 to 60.5 ohms.

Abstract translation: 多层电路板包括第一，第二，第三，第四和第五绝缘基板，第一，第二，第三和第四信号布线层，接地布线层和电源布线层。 绝缘基板和布线层彼此压接，形成约1.0mm厚度的电路板。 第一和第五绝缘基板中的每一个具有从5.225至5.775密耳的厚度。 第二绝缘基板和第四绝缘基板中的每一个具有7.6至8.4密耳的厚度。 第三绝缘基板具有3.8至4.2密耳的厚度。 第一信号布线层相对于接地布线层具有第一电阻。 第二信号布线层相对于接地布线层和电力布线层具有第二电阻。 第三信号布线层相对于接地布线层和电源布线层具有第三电阻。 第四信号布线层相对于电力布线层具有第四电阻。 第一，第二，第三和第四电阻在49.5至60.5欧姆的范围内。

公开(公告)号：US5055969A

公开(公告)日：1991-10-08

申请号：US590233

申请日：1990-09-28

Applicant: John S. Putnam

Inventor： John S. Putnam

IPC: G11B5/48 ,  G11B5/55 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28 ,  H05K3/38

CPC classification number: G11B5/486 ,  G11B5/4846 ,  G11B5/5521 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09327 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K3/281 ,  H05K3/386

Abstract: An improved multilayer flexible circuit for use in a disk storage device actuator arm supporting a data head and a servo head includes a first ground plane and a second electrically floating ground plane.

Abstract translation: 用于支持数据头和伺服头的盘存储装置致动器臂中的改进的多层柔性电路包括第一接地平面和第二电浮动接地平面。

公开(公告)号：US4675789A

公开(公告)日：1987-06-23

申请号：US811355

申请日：1985-12-20

Applicant: Kiyoshi Kuwabara ,  Mikio Nishihara ,  Kazuhisa Tsunoi

Inventor： Kiyoshi Kuwabara ,  Mikio Nishihara ,  Kazuhisa Tsunoi

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K1/14

CPC classification number: H05K1/116 ,  H05K2201/09327 ,  H05K2201/09454 ,  H05K3/429

Abstract: A high density multilayer printed circuit board comprising generally parallel signal layers, electric source layers, and ground layers, with insulating layers arranged between the signal layers and the electric source layers, between the electric source layers and the ground layers, and between the ground layers and the signal layers respectively. Conductor portions are formed in through holes which are opened in a direction transverse to the signal layers, electric source layers, and ground layers. The conductor portions are electrically connected to the signal layers and/or the electric source layers, and/or the ground layers, through the lands thereof, the connections of the lands being substantially equally distributed among the conductor portions.

Abstract translation: 一种高密度多层印刷电路板，包括大致平行的信号层，电源层和接地层，绝缘层布置在信号层和电源层之间，电源层和接地层之间，以及接地层之间 和信号层。 导体部分形成在与信号层，电源层和接地层横向的方向上开放的通孔中。 导体部分通过其平台与信号层和/或电源层和/或接地层电连接，焊盘的连接基本上均匀分布在导体部分之间。

公开(公告)号：US11657862B2

公开(公告)日：2023-05-23

申请号：US16361837

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rogelio Alfonso Moreyra Gonzalez ,  Jose Angel Ramos Martinez ,  James McCall

IPC: G11C5/06 ,  G11C7/22 ,  H05K1/18 ,  H05K1/02 ,  G11C5/04

CPC classification number: G11C7/222 ,  H05K1/0298 ,  H05K1/181 ,  G11C5/04 ,  H05K2201/09227 ,  H05K2201/09327 ,  H05K2201/10159

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

公开(公告)号：US20190214812A1

公开(公告)日：2019-07-11

申请号：US16325407

申请日：2017-08-11

Applicant: GE Aviation Systems Limited

Inventor： David Alan Elliott

IPC: H02H7/20 ,  H05K1/02 ,  H02H1/00

CPC classification number: H02H7/20 ,  B64D2221/00 ,  H02H1/0007 ,  H02H3/05 ,  H03K17/082 ,  H05K1/0254 ,  H05K1/0263 ,  H05K3/46 ,  H05K2201/09327 ,  H05K2201/10053 ,  H05K2201/10181

Abstract: A method and apparatus for arranging fuses in a printed circuit board includes a power input configured to connect to a power source, at least one electrical component connected to the power input, a first output connected to the at least one electrical component and configured to connect to a load, and a fuse disposed between the at least one electrical component and the first output, and having a first trip rating.

公开(公告)号：US20180279466A1

公开(公告)日：2018-09-27

申请号：US15920508

申请日：2018-03-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： RYOSUKE SHIOZAKI ,  YUTO SUZUKI ,  HIDEKI IWAKI

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11 ,  H05K3/42 ,  H01Q1/38

CPC classification number: H05K1/0251 ,  H01P3/08 ,  H01P5/028 ,  H01Q1/38 ,  H01Q21/0075 ,  H01Q21/065 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0248 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10098

Abstract: A circuit board includes: a substrate; a first power feed line disposed so as to be close to a plurality of radiating elements provided on a surface of the substrate and to extend in a first direction; a first connection conductor extending in a second direction orthogonal to the first direction, one end of the first connection conductor being connected to the first power feed line substantially at its central portion in the first direction; and a second power feed line that has a first line part extending in a third direction orthogonal to the second direction, the first line part joining to another end of the first connection conductor, and also has a second line part branching from the first line part, the second line part joining to the other end from a third direction side.