公开(公告)号：US20130199577A1

公开(公告)日：2013-08-08

申请号：US13369138

申请日：2012-02-08

Applicant: I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: B08B7/04 ,  B08B5/00 ,  B08B3/08 ,  B08B3/02 ,  B08B3/12

CPC classification number: H01L21/02041 ,  H01L21/4864 ,  H01L21/67028 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer.

Abstract translation: 助焊剂残渣清洁系统包括第一和第二浸没室，第一和第二喷雾室以及干燥室。 当晶片浸入第一化学品中时，第一浸入室软化在介于晶片和管芯之间的微胶片周围形成的焊剂残余物的外部区域。 当晶片通过第一化学喷雾冲击以便暴露焊剂残余物的内部区域时，第一喷雾室除去焊剂残余物的外部区域。 当晶片浸入第二种化学品中时，第二浸入室软化助焊剂残余物的内部区域。 当晶片被第二化学喷雾冲击时，第二喷雾室去除焊剂残余物的内部区域，以便将晶​​片清洁至预定的标准。 干燥室干燥晶片。

公开(公告)号：US08501590B2

公开(公告)日：2013-08-06

申请号：US13176606

申请日：2011-07-05

Applicant: Chung Yu Wang ,  Kung-Chen Yeh ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Kung-Chen Yeh ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/78

CPC classification number: H01L23/58 ,  H01L21/486 ,  H01L21/673 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.

Abstract translation: 用于在晶片插入件上进行裸片切割的方法和装置。 公开了包括接收包括安装在插入器基板的裸片侧上的一个或多个集成电路管芯并且在集成电路管芯之间的空间中限定的划线区域的插入件组件的方法，所述插入器具有用于接收外部连接器的相对侧; 将所述插入器组件的模具侧安装到带组件上，所述带组件包括粘合带和设置在所述集成电路管芯之间的填充间隙之间的预成型间隔件; 以及通过在所述划线区域中切割所述插入件的相对侧来切割所述插入件组件，以切割所述插入件，所述切口将所述插入件分离成晶片组件上的一个或多个模具。 公开了与该方法一起使用的装置。

公开(公告)号：US20130187270A1

公开(公告)日：2013-07-25

申请号：US13452140

申请日：2012-04-20

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

Abstract translation: 封装包括在管芯的顶表面处具有导电焊盘的芯片，在导电焊盘上方并连接到导电焊盘的柱形凸块，以及重新分配线，并且连接到螺柱凸块。 电连接器在再分配线上电连接。

公开(公告)号：US20130168848A1

公开(公告)日：2013-07-04

申请号：US13338820

申请日：2011-12-28

Applicant: Jing-Cheng LIN ,  Jui-Pin HUNG ,  Nai-Wei LIU ,  Yi-Chao MAO ,  Wan-Ting SHIH ,  Tsan-Hua TUNG

Inventor： Jing-Cheng LIN ,  Jui-Pin HUNG ,  Nai-Wei LIU ,  Yi-Chao MAO ,  Wan-Ting SHIH ,  Tsan-Hua TUNG

IPC: H01L23/498 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

Abstract translation: 提供了在半导体器件基板上形成模制化合物以使得晶片级封装（WLP）中的扇出结构能够实现的机制。 这些机构涉及覆盖围绕接触垫的绝缘层的表面的部分。 这些机制提高了包装的可靠性和包装过程的过程控制。 这些机理还降低了界面分层的风险，并且在后续处理过程中绝缘层过度消除气泡。 这些机制进一步改善了平面化终点。 通过利用接触焊盘和绝缘层之间的保护层，可以减少铜外扩散，并且还可以提高接触焊盘和绝缘层之间的粘附。

公开(公告)号：US20130140690A1

公开(公告)日：2013-06-06

申请号：US13311692

申请日：2011-12-06

Applicant: Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

公开(公告)号：US20130134582A1

公开(公告)日：2013-05-30

申请号：US13427753

申请日：2012-03-22

Applicant: Chen-Hua YU ,  Jing-Cheng LIN

Inventor： Chen-Hua YU ,  Jing-Cheng LIN

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13564 ,  H01L2224/1412 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/381

Abstract: The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package.

Abstract translation: 用于形成描述的多芯片封装的机构使得具有不同凸块尺寸的芯片被封装到公共衬底。 具有较大凸块的芯片可以与衬底上的两个或更多个更小的凸块接合。 相反，芯片上的两个或更多个小凸块可以与基板上的大凸块粘合。 通过允许具有不同尺寸的凸块结合在一起，具有不同凸块尺寸的芯片可以封装在一起以形成多芯片封装。

公开(公告)号：US20130134559A1

公开(公告)日：2013-05-30

申请号：US13397204

申请日：2012-02-15

Applicant: Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

Inventor： Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

公开(公告)号：US20130119533A1

公开(公告)日：2013-05-16

申请号：US13297992

申请日：2011-11-16

Applicant: Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract translation: 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。

公开(公告)号：US20130087920A1

公开(公告)日：2013-04-11

申请号：US13270776

申请日：2011-10-11

Applicant: Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L23/488 ,  H01L21/50

CPC classification number: H01L24/16 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16258 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/05552

Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.

Abstract translation: 实施例是包括基板，第一模具和第二模具的结构。 衬底具有第一表面。 第一模具通过第一电连接器附接到基板的第一表面。 第二模具通过第二电连接器附接到基板的第一表面。 第二电连接器之一的尺寸小于第一电连接器之一的尺寸。

公开(公告)号：US08395215B2

公开(公告)日：2013-03-12

申请号：US13351824

申请日：2012-01-17

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02175 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

Abstract: Germanium field effect transistors and methods of fabricating them are described. In one embodiment, the method includes forming a germanium oxide layer over a substrate and forming a metal oxide layer over the germanium oxide layer. The germanium oxide layer and the metal oxide layer are converted into a first dielectric layer. A first electrode layer is deposited over the first dielectric layer.

Abstract translation: 描述锗场效应晶体管及其制造方法。 在一个实施例中，该方法包括在衬底上形成氧化锗层并在氧化锗层上形成金属氧化物层。 氧化锗层和金属氧化物层被转换为第一电介质层。 第一电极层沉积在第一介电层上。