公开(公告)号：US07871919B2

公开(公告)日：2011-01-18

申请号：US12344802

申请日：2008-12-29

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05556 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands.

摘要翻译： 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该方法包括在延伸到下面的金属层的电介质层中形成多个沟槽。 该方法还包括在多个沟槽中沉积金属以形成与下面的金属层接触的离散金属线岛。 该方法还包括形成与多个金属线岛电连接的焊料凸块。

公开(公告)号：US07863734B2

公开(公告)日：2011-01-04

申请号：US12186655

申请日：2008-08-06

申请人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L23/34 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

摘要翻译： 一种电子装置和包装电子装置的方法。 该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘 电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

公开(公告)号：US07862987B2

公开(公告)日：2011-01-04

申请号：US11942753

申请日：2007-11-20

申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC分类号： G03F7/26

CPC分类号： H01L21/0272 ,  G03F7/095 ,  G03F7/168 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047

摘要： An electrical structure and method of forming. The method comprises providing a substrate structure. A first layer comprising a first photosensitive material having a first polarity is formed over and in contact with the substrate structure. A second layer comprising photosensitive material having a second polarity is formed over and in contact with the first layer. The first polarity comprises an opposite polarity as the second polarity. Portions of the first and second layers are simultaneously exposed to a photo exposure light source. The portions of the first and second layers are developed such that structures are formed.

摘要翻译： 一种电气结构和成型方法。 该方法包括提供衬底结构。 包括具有第一极性的第一感光材料的第一层形成在衬底结构上并与衬底结构接触。 包含具有第二极性的感光材料的第二层形成在第一层之上并与第一层接触。 第一极性包括与第二极性相反的极性。 第一层和第二层的一部分同时暴露于曝光光源。 第一层和第二层的部分被显影以形成结构。

公开(公告)号：US07704804B2

公开(公告)日：2010-04-27

申请号：US11953363

申请日：2007-12-10

申请人： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

发明人： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/82

CPC分类号： H01L23/5258 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/12 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/05552

摘要： A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.

摘要翻译： 在相邻熔丝结构之间的低k电介质或氧化硅层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。 通过使用与形成互连结构同时形成的导电材料的蚀刻停止形状将钝化层固定就位。 这产生了可靠且可重复的熔丝结构，其在容易制造的熔丝结构上具有可控钝化层。

公开(公告)号：US07614147B2

公开(公告)日：2009-11-10

申请号：US12138531

申请日：2008-06-13

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01K3/10

CPC分类号： H01L23/544 ,  H01L22/24 ,  H01L22/32 ,  H01L22/34 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49227 ,  H01L2224/45099

摘要： An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.

摘要翻译： 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。

公开(公告)号：US20090273081A1

公开(公告)日：2009-11-05

申请号：US12113230

申请日：2008-05-01

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls.

摘要翻译： 一种控制崩溃芯片连接（C4）方法和用于无铅焊料球的集成电路结构，通过在焊球下方放置软厚的绝缘垫，并将焊料球的金属化 衬垫的集成电路不接触，但在焊球的间距内。

公开(公告)号：US20090235212A1

公开(公告)日：2009-09-17

申请号：US12046608

申请日：2008-03-12

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.

摘要翻译： 提供了故障分析工具，使用该工具的方法和设计用于设计用于保护封装期间半导体芯片中的接线故障的关键区域的掩模的设计结构。 故障分析工具包括计算机基础设施，其可操作以通过确定从芯片的中心到焊料凸块处理的位置的距离来确定在焊料凸块形成期间的布线层故障的风险区域，并且识别位置边缘处的区域 用于从芯片的中心预定距离和更大的焊料凸块工艺。

公开(公告)号：US07517789B2

公开(公告)日：2009-04-14

申请号：US11869787

申请日：2007-10-10

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L23/3171 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer includes a hole and a trench, wherein the hole is directly above the electrically conductive bond pad, and wherein the trench is not filled by any electrically conductive material; and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad.

摘要翻译： 一种焊料凸块结构及其形成方法。 该结构包括（a）包括电介质层顶表面的电介质层（b）与电介质层顶表面直接物理接触的导电接合焊盘; （c）电介质层顶表面上的图案化支撑/界面层，并且在参考方向上比导电接合焊盘厚，其中图案化支撑/界面层包括孔和沟槽，其中孔直接位于电气 导电接合焊盘，并且其中所述沟槽不被任何导电材料填充; 和（d）填充该孔并电耦合到导电接合焊盘的导电焊料凸块。

公开(公告)号：US20090057908A1

公开(公告)日：2009-03-05

申请号：US11849409

申请日：2007-09-04

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/49

CPC分类号： H01L24/03 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014

摘要： A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

摘要翻译： 引线接合焊盘和制造引线接合焊盘的方法。 该方法包括：提供衬底; 在所述基板的顶表面上形成导电层; 将导电层图案化成间隔开的多个引线接合焊盘; 以及在相邻引线接合焊盘之间的空间中在基板的顶表面上形成保护电介质层，在与键合焊盘的共面顶表面共面的空间中的电介质层的顶表面。

公开(公告)号：US20090032909A1

公开(公告)日：2009-02-05

申请号：US11833348

申请日：2007-08-03

申请人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

发明人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC分类号： H01L23/58 ,  H01L21/64

CPC分类号： H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

摘要： Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

摘要翻译： 结构及其形成方法。 该结构包括半导体衬底，半导体衬底上的晶体管和半导体衬底顶部的N个互连层，N为正整数。 晶体管电耦合到N个互连层。 该结构还包括在N个互连层的顶部上的第一介电层和在第一介电层的顶部上的P个裂纹停止区，P是正整数。 该结构还包括在第一电介质层的顶部上的第二电介质层。 P裂纹停止区域的每个裂纹停止区域被第一介电层和第二介电层完全包围。 该结构还包括在第二电介质层的顶部上的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。