公开(公告)号：US20180323199A1

公开(公告)日：2018-11-08

申请号：US15973697

申请日：2018-05-08

Applicant: Micron Technology, Inc.

Inventor： Martin C. Roberts ,  Sanh D. Tang ,  Fred D. Fishburn

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L49/02 ,  H01L23/528 ,  H01L29/423 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514

CPC classification number: H01L27/10805 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32134 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42376

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

公开(公告)号：US20180323142A1

公开(公告)日：2018-11-08

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US10083734B1

公开(公告)日：2018-09-25

申请号：US15804981

申请日：2017-11-06

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06

CPC classification number: G11C11/4023 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/4097 ,  G11C2207/105 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10855 ,  H01L27/10885

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US10069067B2

公开(公告)日：2018-09-04

申请号：US15857448

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

公开(公告)号：US20180114901A1

公开(公告)日：2018-04-26

申请号：US15848399

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US09812455B2

公开(公告)日：2017-11-07

申请号：US15218487

申请日：2016-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

IPC: H01L27/108 ,  H01L21/768 ,  H01L49/02 ,  H01L21/3213

CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

公开(公告)号：US09780115B2

公开(公告)日：2017-10-03

申请号：US15188273

申请日：2016-06-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11548 ,  H01L27/11575 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L45/00

CPC classification number: H01L27/11582 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C2213/71 ,  H01L21/28273 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/06

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US09741737B1

公开(公告)日：2017-08-22

申请号：US15130803

申请日：2016-04-15

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US09520558B2

公开(公告)日：2016-12-13

申请号：US13961479

申请日：2013-08-07

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US20160300842A1

公开(公告)日：2016-10-13

申请号：US14681884

申请日：2015-04-08

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir ,  Dylan R. MacMaster

IPC: H01L27/108 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L27/10805 ,  H01L21/02068 ,  H01L21/31111 ,  H01L21/743 ,  H01L21/762 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649 ,  H01L29/7391

Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars. Semiconductor device structures and additional methods are also described.

Abstract translation: 形成用于半导体器件结构的触点的方法包括形成延伸到相邻的半导体柱中的接触孔，并形成氮化物覆盖的电极的氮化物材料。 复合结构形成在接触孔内并且包括在接触孔的侧壁上的氧化物结构和氧化物结构上的氮化物结构。 导电结构形成在复合结构的内侧壁上。 附加的氮化物封盖的电极形成在导电结构之上并垂直于氮化物封盖的电极延伸。 一对氮化物间隔物形成在另外的氮化物覆盖的电极的相对侧壁上，并且通过延伸到相邻半导体柱的一部分的上表面的孔与相邻的氮化物间隔物相分离。 去除部分氧化物结构以暴露相邻半导体柱的部分的侧壁。 还描述了半导体器件结构和附加方法。