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    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
    133.
    发明申请
    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY 有权
    包含频率变化检测电路的集成电路

    公开(公告)号：US20150333740A1

    公开(公告)日：2015-11-19

    申请号：US14808936

    申请日：2015-07-24

    Applicant: Rambus Inc.

    Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

    IPC: H03K3/012 ,  G11C7/22 ,  H03L7/24

    CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

    Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

    Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
    138.
    发明申请
    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY 有权
    包含频率变化检测电路的集成电路

    公开(公告)号：US20140070854A1

    公开(公告)日：2014-03-13

    申请号：US13839059

    申请日：2013-03-15

    Applicant: RAMBUS INC.

    Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

    Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

    Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

    ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION
    139.
    发明申请
    ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION 审中-公开
    多线通信期间的错误检测和偏移消除

    公开(公告)号：US20130346822A1

    公开(公告)日：2013-12-26

    申请号：US13914091

    申请日：2013-06-10

    Applicant: Rambus Inc.

    Inventor： Jade M. Kizer ,  John Wilson ,  Lei Luo ,  Frederick A. Ware ,  Jared L. Zerbe

    IPC: H03M13/47

    CPC classification number: H03M13/47 ,  H04L25/4919

    Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

    Abstract translation: 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 此外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡以及M个符号集合中的第二值的实例的数量，并且如果不平衡是 检测到，这会导致错误条件。

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