公开(公告)号：US20080265437A1

公开(公告)日：2008-10-30

申请号：US11884613

申请日：2006-03-08

Applicant: Tsukasa Shiraishi ,  Yukihiro Ishimaru ,  Seiji Karashima ,  Seiichi Natkatani ,  Hiroki Yabe

Inventor： Tsukasa Shiraishi ,  Yukihiro Ishimaru ,  Seiji Karashima ,  Seiichi Natkatani ,  Hiroki Yabe

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17132 ,  H01L2224/17136 ,  H01L2224/17151 ,  H01L2224/17155 ,  H01L2224/17177 ,  H01L2224/17515 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83007 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83887 ,  H01L2224/83888 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/09781 ,  H05K2201/10977 ,  H05K2203/046 ,  Y02P70/613 ,  H01L2224/1713 ,  H01L2224/1715 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (100) comprising a semiconductor chip (10) and a mounting substrate (30), a plurality of electrode terminals (12) are formed on the surface (10a) of the semiconductor chip (10) opposing the mounting substrate side, connection terminals (32) respectively corresponding to the plurality of electrode terminals (12), are formed on the mounting substrate (30), the connection terminals (32) on the mounting substrate (30) and the electrode terminals (12) are electrically connected collectively by solder bumps (17) formed in self-assembly, an electrode pattern (20) not connected with the electrode terminals (12) and the connection terminals (32) is formed on the chip surface (10a) or the surface (35) of the mounting substrate (30) corresponding to the chip surface (10a), and solder (19) is accumulated on the electrode pattern (20).

Abstract translation: 具有半导体芯片的高可靠性，高生产率的封装及其制造方法。 在包括半导体芯片（10）和安装基板（30）的封装（100）中，在与安装基板侧相对的半导体芯片（10）的表面（10a）上形成多个电极端子（12） 分别对应于多个电极端子（12）的连接端子（32）形成在安装基板（30）上，安装基板（30）和电极端子（12）之间的连接端子（32）是电气 在自组装中形成的焊料凸点（17）共同连接，在芯片表面（10a）或表面（10a）上形成未与电极端子（12）和连接端子（32）连接的电极图案（20） 35）对应于芯片表面（10a），并且焊料（19）积聚在电极图案（20）上。

公开(公告)号：US20080203564A1

公开(公告)日：2008-08-28

申请号：US12068438

申请日：2008-02-06

Applicant: Souichirou Motoyoshi ,  Hirokazu Honda

Inventor： Souichirou Motoyoshi ,  Hirokazu Honda

IPC: H01L23/488 ,  H01L21/56 ,  H05K1/00

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/18301 ,  H05K3/305 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a wiring substrate, a semiconductor chip, a conductive bump, and an under-fill resin. The wiring substrate has a solder resist layer, and a stress alleviating portion. The stress alleviating portion is mounted on the solder resist layer opposed to the outer circumference of the semiconductor chip. The material of the stress alleviating portion is different from that of the solder resist layer. The stress alleviating portion alleviates the stress acting on the solder resist layer and the under-fill resin. The semiconductor chip is mounted above the wiring substrate via the conductive bump. The gap between the wiring substrate and the semiconductor chip is filled with the under-fill resin.

Abstract translation: 半导体器件具有布线基板，半导体芯片，导电凸块和欠填充树脂。 布线基板具有阻焊层和应力减轻部。 应力减轻部安装在与半导体芯片的外周相对的阻焊层上。 应力缓解部的材料与阻焊层的材质不同。 应力减轻部分减轻作用在阻焊层和未填充树脂上的应力。 半导体芯片通过导电凸块安装在布线基板上。 配线基板和半导体芯片之间的间隙填充有未填充树脂。

公开(公告)号：US20080173997A1

公开(公告)日：2008-07-24

申请号：US11983868

申请日：2007-11-13

Applicant: Hiroshi Kobayashi

Inventor： Hiroshi Kobayashi

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H05K1/0271 ,  G06K19/0723 ,  H01L21/563 ,  H01L23/4985 ,  H01L23/49855 ,  H01L24/12 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/189 ,  H05K3/305 ,  H05K3/3494 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2009 ,  H05K2203/0195 ,  H05K2203/0278 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of manufacturing an electronic device includes the steps of: forming a conductive pattern on a film made of a resin material and thereby forming a base body on which a circuit chip is mounted; forming a reinforcing layer that suppresses expansion and contraction of the film in either one of a mounting area on the film which area the circuit chip is mounted on and a rear area at the back of the mounting area; applying a thermosetting adhesive; mounting the circuit chip; pinching the base body mounted with the circuit chip by a heating device that heats the thermosetting adhesive and has a pressing section and a supporting section; and fixing the circuit chip to the conductive pattern by hardening the thermosetting adhesive through heating by the heating device.

Abstract translation: 一种制造电子器件的方法包括以下步骤：在由树脂材料制成的膜上形成导电图案，从而形成其上安装有电路芯片的基体; 在安装有电路芯片的区域的膜的安装区域和安装区域的背面的后部区域中形成抑制膜的膨胀和收缩的增强层; 涂上热固性粘合剂; 安装电路芯片; 通过加热装置夹住安装有电路芯片的基体，并且具有加压部分和支撑部分; 并且通过加热装置的加热硬化热固性粘合剂将电路芯片固定到导电图案上。

公开(公告)号：US20080165518A1

公开(公告)日：2008-07-10

申请号：US11886311

申请日：2006-03-13

Applicant: Takashi Ichiryu ,  Seiichi Nakatani ,  Seiji Karashima ,  Yoshihiro Tomita ,  Koichi Hirano ,  Toshio Fujii

Inventor： Takashi Ichiryu ,  Seiichi Nakatani ,  Seiji Karashima ,  Yoshihiro Tomita ,  Koichi Hirano ,  Toshio Fujii

IPC: H01L23/498 ,  H05K3/36 ,  B23K1/20 ,  H01L21/60

CPC classification number: H05K3/3436 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1152 ,  H01L2224/11524 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83886 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow. As a result, the molten solder powder is allowed to self-assemble and grow in the vicinity of the electrically-conductive particles, which leads to a formation of connections or bumps.

Abstract translation: 根据本发明的倒装芯片安装工艺或凸块形成工艺的特征在于，导电颗粒固定在形成在电子部件上的电极上。 将包含焊料粉末，对流添加剂和树脂组分的组合物供应到电子部件的表面上，该表面设置有电极。 将所提供的组合物加热到使焊料粉末熔化的温度。 结果，对流添加剂沸腾或分解以产生气体。 所产生的气体在所提供的组合物内产生对流现象。 由于对流现象促使焊料粉末的移动，焊料粉末可以在组合物内自由移动。 导电颗粒用作焊料粉末的自组装和生长的核。 结果，允许熔融焊料粉末在导电颗粒附近自组装和生长，这导致连接或凸块的形成。

公开(公告)号：US20080145589A1

公开(公告)日：2008-06-19

申请号：US11870620

申请日：2007-10-11

Applicant: Chih Pin Hung ,  Chi Tsung Chiu ,  In De Ou ,  Yung Hui Wang

Inventor： Chih Pin Hung ,  Chi Tsung Chiu ,  In De Ou ,  Yung Hui Wang

IPC: B32B1/02

CPC classification number: H05K1/144 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K2201/042 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T428/23 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An electronic package is provided. The electronic package includes a first substrate, an electronic component, a first sealant, a second substrate, a plurality of bonding wires and a second sealant, wherein the first substrate has opposing upper and lower surfaces and a plurality of bonding pads is disposed on the upper surface of the first substrate. The electronic component is positioned on the upper surface of the first substrate and electrically connected to the bonding pads. The first sealant is formed on the upper surface of the first substrate to encapsulate the electronic component. The lower surface of the second substrate is attached to the first sealant. The upper surface of the second substrate includes a central protrusion and a rim portion which surrounds and is lower than the central protrusion. A plurality of bonding wires is used to electrically connect the rim portion to the first substrate. The second sealant is formed on the upper surface of the first substrate and on the rim portion of the second substrate to encapsulate the bonding wires, the first sealant and the rim portion.

Abstract translation: 提供电子包装。 电子封装包括第一基板，电子部件，第一密封剂，第二基板，多个接合线和第二密封剂，其中第一基板具有相对的上表面和下表面，并且多个接合焊盘设置在 第一基板的上表面。 电子部件位于第一基板的上表面上并电连接到接合焊盘。 第一密封剂形成在第一基板的上表面上以封装电子部件。 第二基板的下表面附接到第一密封剂。 第二基板的上表面包括中心突起和围绕中心突起的边缘部分。 使用多个接合线将边缘部分电连接到第一基板。 第二密封剂形成在第一基板的上表面和第二基板的边缘部分上，以封装接合线，第一密封剂和边缘部分。

公开(公告)号：US20080130241A1

公开(公告)日：2008-06-05

申请号：US11606750

申请日：2006-11-30

Applicant: Mohan R. Nagar ,  Kuo-Chuan Liu ,  Mudasir Ahmad ,  Bangalore J. Shanker ,  Jie Xue

Inventor： Mohan R. Nagar ,  Kuo-Chuan Liu ,  Mudasir Ahmad ,  Bangalore J. Shanker ,  Jie Xue

IPC: H05K7/20 ,  H05K3/34

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.

Abstract translation: 一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。 沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件的接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

公开(公告)号：US07380337B2

公开(公告)日：2008-06-03

申请号：US11378826

申请日：2006-03-17

Applicant: Kaoru Soeta

Inventor： Kaoru Soeta

IPC: H05K3/30

CPC classification number: H05K3/326 ,  G01R1/0483 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81899 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/305 ,  H05K3/4092 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/162 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A first cavity in a holder is provided with a plurality of spiral contactors and a thermosetting adhesive member. In a state where a first bare chip is mounted in the first cavity and spherical contactors on the first bare chip are pressed against the plurality of spiral contactors, various tests are performed. If the result of the test is pass, the holder is heated so that the adhesive member becomes hard and rigid by being heated. This can perform securing while a good connection between the first bare chip and the holder is maintained. If the result of the test is fail, only the first bare chip is removed and replaced with a new bare chip.

Abstract translation: 保持器中的第一空腔设置有多个螺旋接触器和热固性粘合构件。 在第一裸芯片安装在第一空腔中的状态下，第一裸芯片上的球形接触器被压靠在多个螺旋接触器上，进行各种测试。 如果测试结果通过，则保持器被加热，使得粘合构件通过加热而变硬和刚性。 这可以在保持第一裸芯片和保持器之间的良好连接的同时执行固定。 如果测试结果失败，只有第一个裸芯片被移除，并用新的裸芯片替换。

公开(公告)号：US20080116588A1

公开(公告)日：2008-05-22

申请号：US11632609

申请日：2005-07-12

Applicant: Marcus H. Van Kleef ,  Rene W. J. M. Van Den Boomem

Inventor： Marcus H. Van Kleef ,  Rene W. J. M. Van Den Boomem

IPC: H01L23/498 ,  H05K3/34 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09481 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The assembly comprises an electronic device (20) that is attached to a first side (11) of a carrier substrate (10) with solder connections (18). The first side (11) of the substrate (10) is provided with bond pads (15) and a solder resist layer (16). The space between the substrate (10) and the electronic device (20) is filled with an encapsulant (19) The substrate (10) further comprises contact pads for connection to an external board. The solder resist layer (16) is patterned according to a pattern that includes an aperture (161) adjacent to a first bond pad (15). This aperture (161) is ring-shaped and forms the circumference of the first bond pad. Herewith, delamination is prevented, also if a via (142) is present in the substrate (10) below the bond pad (15).

Abstract translation: 组件包括电子器件（20），其通过焊料连接（18）附接到载体衬底（10）的第一侧面（11）。 衬底（10）的第一侧（11）设置有接合焊盘（15）和阻焊层（16）。 衬底（10）和电子器件（20）之间的空间填充有密封剂（19）。衬底（10）还包括用于连接到外部板的接触焊盘。 阻焊层（16）根据包括与第一接合焊盘（15）相邻的孔（161）的图案被图案化。 该孔（161）是环形的并且形成第一接合焊盘的圆周。 因此，如果在接合焊盘（15）下方的衬底（10）中存在通孔（142），则防止分层。

公开(公告)号：US20080116552A1

公开(公告)日：2008-05-22

申请号：US11560867

申请日：2006-11-17

Applicant: James Rose ,  Robert Lewandowski ,  Thomas Gorczyca ,  Kevin Durocher ,  Jonathan Short ,  Donna Sherman

Inventor： James Rose ,  Robert Lewandowski ,  Thomas Gorczyca ,  Kevin Durocher ,  Jonathan Short ,  Donna Sherman

IPC: H01L23/02

CPC classification number: H05K3/361 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/244 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0495 ,  H01L2924/00

Abstract: An electronic system (1) having an interconnect structure (30, 45). In one embodiment a system (1) includes a first electronic device (2) with a first plurality of contact pads (15) each having a noble metal (18) formed along a first surface (19), and a second electronic device (3) with a second plurality of contact pads (29) each having a noble metal (18) formed along a first surface (19). The noble metal (18) of one of the contact pads (15) of the first device (2) is bonded to the noble metal (18) of one of the contact pads (29) of the second device (3). In one embodiment of an associated method of forming an interconnect structure (45), a first electronic device (2) is provided with a first plurality of contact pads (15) each having a noble metal (18) along a first surface (19), and a second electronic device (3) is provided with a plurality of contact pads (29) each having a noble metal (18) along a first surface (19). One or more of the contact pads (15) on the first device (2) is aligned with one or more of the contact pads (29) on the second device (3) to form pairs of pads (45) for electrical contact with one another. The first surface (19) of a contact pad (15) of the first device (2) is pressed against the first surface (19) of a contact pad (29) on the second device (3) to make contact between the two first surfaces (19).

Abstract translation: 一种具有互连结构（30,45）的电子系统（1）。 在一个实施例中，系统（1）包括具有第一多个接触焊盘（15）的第一电子设备（2），每个接触焊盘具有沿着第一表面（19）形成的贵金属（18）和第二电子设备（3） ）与具有沿着第一表面（19）形成的贵金属（18）的第二多个接触焊盘（29）连接。 第一装置（2）的接触焊盘（15）之一的贵金属（18）被接合到第二装置（3）的接触焊盘（29）之一的贵金属（18）上。 在形成互连结构（45）的相关联的方法的一个实施例中，第一电子器件（2）设置有第一多个接触焊盘（15），每个接触焊盘沿着第一表面（19）具有贵金属（18） ，并且第二电子设备（3）设置有多个接触焊盘（29），每个接触焊盘（29）沿着第一表面（19）具有贵金属（18）。 第一装置（2）上的接触焊盘（15）中的一个或多个与第二装置（3）上的一个或多个接触焊盘（29）对准以形成一对焊盘（45），用于与一个 另一个。 第一装置（2）的接触垫（15）的第一表面（19）被压靠在第二装置（3）上的接触垫（29）的第一表面（19）上，以使第一装置 表面（19）。

公开(公告)号：US20080111216A1

公开(公告)日：2008-05-15

申请号：US11860556

申请日：2007-09-25

Applicant: Michael BAUER ,  Alfred HAIMERL ,  Angela KESSLER ,  Joachim MAHLER ,  Wolfgang SCHOBER

Inventor： Michael BAUER ,  Alfred HAIMERL ,  Angela KESSLER ,  Joachim MAHLER ,  Wolfgang SCHOBER

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H05K3/284 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49531 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/142 ,  H05K2201/09063 ,  H05K2201/09072 ,  H05K2201/1034 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A component arrangement comprising a carrier, a component in a housing with electrical contacts and a moulding compound that encloses the carrier, the semiconductor component in the housing and the electrical contacts, wherein the component is applied on the carrier, and wherein the carrier is provided with holes, and a method for producing a component arrangement, wherein the carrier is provided with holes, the component is positioned on the carrier, the component is connected to the carrier, the component with the carrier is positioned in the leadframe, and this arrangement is enclosed by a moulding compound.

Abstract translation: 一种部件装置，包括载体，具有电触头的壳体中的部件和封装载体的模制化合物，壳体中的半导体部件和电触点，其中将部件施加在载体上，并且其中提供载体 具有孔，以及用于制造部件布置的方法，其中，所述载体设置有孔，所述部件位于所述载体上，所述部件连接到所述载体，所述部件与所述载体位于所述引线框架中，并且所述布置 被模塑料包围。