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    Using dynamic bursts to support frequency-agile memory interfaces
    164.
    发明授权
    Using dynamic bursts to support frequency-agile memory interfaces 有权
    使用动态突发来支持频率敏捷存储器接口

    公开(公告)号：US09568980B2

    公开(公告)日：2017-02-14

    申请号：US14416088

    申请日：2013-09-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

    IPC: G06F1/32 ,  G06F1/00 ,  G06F13/16

    CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

    Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

    Abstract translation: 所公开的实施例涉及支持动态突发以促进存储器控制器和存储器设备之间的频率敏捷通信的系统。 在操作期间，系统监视在存储器件和存储器控制器之间的接口处接收到的参考时钟信号。 在检测到从全速率到子速率的参考时钟信号中的频率变化时，接口以突发模式操作，其中数据通过由接口的部分断电的中间的低功率间隔分开的脉冲串传送。

    Clock generation for timing communications with ranks of memory devices
    165.
    发明授权
    Clock generation for timing communications with ranks of memory devices 有权
    用于与存储器设备等级进行定时通信的时钟生成

    公开(公告)号：US09563228B2

    公开(公告)日：2017-02-07

    申请号：US14954940

    申请日：2015-11-30

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F1/04 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  H04L7/033 ,  G11C7/04

    CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

    Abstract translation: 存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。 第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。 定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位 设备。

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