公开(公告)号：US08018026B2

公开(公告)日：2011-09-13

申请号：US12564190

申请日：2009-09-22

Applicant: Yasutaka Nakashiba

Inventor： Yasutaka Nakashiba

IPC: H01L29/00

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0233 ,  H05K1/111 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/09809 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

Abstract translation: 一种半导体器件，包括：半导体衬底; 形成在所述半导体衬底上的多层互连结构; 布置在多层互连结构的表面上的用于倒装芯片封装的端子; 以及形成为在不与螺旋电感器电连接的平面图中包围用于倒装芯片封装的端子的螺旋电感器。 可以提供螺旋电感器用于峰化，通过该峰值，可以补偿在高频率下引起的增益减小。

公开(公告)号：US20110099803A1

公开(公告)日：2011-05-05

申请号：US12986447

申请日：2011-01-07

Applicant: Adam W. Gibson ,  Jeffrey Alan Poulsen

Inventor： Adam W. Gibson ,  Jeffrey Alan Poulsen

IPC: H05K3/00

CPC classification number: H05K1/0225 ,  H05K1/0216 ,  H05K1/0228 ,  H05K1/024 ,  H05K3/0044 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/10189 ,  Y10T29/49124

Abstract: A method of improving electrical isolation between a first circuit and a second circuit sharing a common substrate having an effective dielectric constant greater than that of air. The first and second circuits are spaced apart and separated from one another by an intermediate portion of the substrate. The method includes removing a portion of the intermediate portion to replace the portion removed with air thereby reducing the effective dielectric constant of the intermediate portion. By reducing the effective dielectric constant of the intermediate portion, electrical isolation between the first and second circuits is improved thereby reducing crosstalk between the first and second circuits. In particular implementations, the method may be used to reduce alien crosstalk between adjacent communication outlets in a patch panel.

Abstract translation: 一种改善第一电路和共享具有大于空气的有效介电常数的公共衬底的第二电路之间的电隔离的方法。 第一和第二电路间隔开并且通过衬底的中间部分彼此分离。 该方法包括去除中间部分的一部分以取代用空气除去的部分，从而降低中间部分的有效介电常数。 通过降低中间部分的有效介电常数，改善第一和第二电路之间的电隔离，从而减少第一和第二电路之间的串扰。 在具体的实现中，该方法可以用于减少接线板中的相邻通信插座之间的外来串扰。

公开(公告)号：US07911049B2

公开(公告)日：2011-03-22

申请号：US12171602

申请日：2008-07-11

Applicant: Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

Inventor： Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

IPC: H01L23/053

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

Abstract translation: 提供了用于多层互连基板中的高速信号的电学优化和结构保护的微通孔结构。 通孔结构消除了与参考平面的接触的重叠，从而减小了通孔电容，从而减小了通孔结构中的通路阻抗失配。 结果，通孔结构被电学优化。 通孔结构还包括一个或多个浮动支撑构件，该浮动支撑构件在通孔和参考平面之间的通孔间隙区域内靠近通孔放置。 浮动支撑构件在它们不与通孔或参考平面电接触的意义上是“浮动的”。 因此，它们不是用于信号传播的目的，而是仅用于结构支持。 浮动支撑构件可以通过一个或多个微孔结构彼此连接。

公开(公告)号：US07854368B2

公开(公告)日：2010-12-21

申请号：US11923413

申请日：2007-10-24

Applicant: Young Hoon Kwark ,  Christian Schuster

Inventor： Young Hoon Kwark ,  Christian Schuster

IPC: B23K31/02

CPC classification number: H01L24/46 ,  H01L23/66 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/43 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49174 ,  H01L2224/8502 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0219 ,  H05K1/0243 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/1028 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method (and structure) of making an electronic interconnection, includes, for a signal line to be interconnected, using a plurality of bonding wires configured to provide a controlled impedance effect.

Abstract translation: 制造电子互连的方法（和结构）包括用于要互连的信号线，使用被配置为提供受控阻抗效应的多个接合线。

公开(公告)号：US07684204B2

公开(公告)日：2010-03-23

申请号：US12155583

申请日：2008-06-06

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H05K7/00

CPC classification number: H01L23/50 ,  H01G4/35 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad. The first via is disposed adjacent to the third pad relative to a central line of the first pad, the second via is disposed adjacent to the third pad relative to a central line of the second pad, one or more of the third vias are disposed adjacent to the first via relative to a central line of the third pad, and the rest of the third vias are disposed adjacent to the second via relative to the central line of the third pad.

Abstract translation: 一种电路板，包括：具有用于安装具有第一极性的第一和第二外部电极和第二极性的第三外部电极的垂直多层片状电容器的安装区域的基板; 布置在安装区域上的第一至第三焊盘，第一和第二焊盘具有第一极性并且在安装区域上彼此分开设置，第三焊盘具有第二极性并且设置在第一焊盘和第二焊盘之间以连接到 第三外部电极; 至少一个第一通孔，其形成在所述基板中并连接到所述第一焊盘; 至少一个第二通孔，形成在所述衬底中并连接到所述第二衬垫; 以及形成在基板中并连接到第三焊盘的多个第三通孔。 第一通孔相对于第一焊盘的中心线设置成与第三焊盘相邻，第二通孔相对于第二焊盘的中心线设置为与第三焊盘相邻，第一通孔中的一个或多个邻近 相对于第三焊盘的中心线移动到第一通孔，并且第三通孔的其余部分相对于第三焊盘的中心线设置成与第二通孔相邻。

公开(公告)号：US07566952B2

公开(公告)日：2009-07-28

申请号：US11029518

申请日：2005-01-05

Applicant: Brian A. Floyd ,  Ullrich R. Pfeiffer ,  Scott K. Reynods

Inventor： Brian A. Floyd ,  Ullrich R. Pfeiffer ,  Scott K. Reynods

IPC: H01L23/525

CPC classification number: H05K1/111 ,  H01L23/5225 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06051 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19051 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P5/02 ,  H05K1/0237 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/09781 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Shielded circuit pad is provided where the parasitic capacitance is tuned out by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave applications. The circuit pad is located on the substrate, with a shield located beneath the circuit pad, and the shunt transmission line stub attached to the circuit pad. Accordingly, controlled impedance is obtained for millimeter-wave applications. The spacing between the circuit pad and the shield may then be minimized.

Abstract translation: 提供屏蔽电路板，其中寄生电容通过包括分流传输线短截线来调谐，从而减小了毫米波应用中的衬底感应损耗。 电路板位于基板上，屏蔽层位于电路板下方，并且分流传输线插脚连接到电路板。 因此，对于毫米波应用获得受控阻抗。 然后可以最小化电路板和屏蔽之间的间隔。

公开(公告)号：US07498696B2

公开(公告)日：2009-03-03

申请号：US10993777

申请日：2004-11-20

Applicant: Senthil Kumar Sundaram

Inventor： Senthil Kumar Sundaram

IPC: H04B3/00

CPC classification number: H05K1/0218 ,  H05G1/10 ,  H05K1/0254 ,  H05K1/18 ,  H05K2201/0792 ,  H05K2201/09781 ,  H05K2201/10022 ,  H05K2201/10553

Abstract: In some embodiments, a voltage grading and shielding method for a high voltage component, is provided. In some embodiments, the method includes configuring at least one first track constructed of a metal or an alloy, at a first location predetermined from the mounting position of the high voltage component, and at least one second track constructed of a metal or an alloy thereof, at a second location predetermined along the length of the high voltage component. In some embodiments, the configured at least one first track substantially reduces the stray capacitance effect and the at least one second track produces a substantially linear voltage distribution along the length of the high voltage component.

Abstract translation: 在一些实施例中，提供了用于高电压部件的电压分级和屏蔽方法。 在一些实施例中，该方法包括在从高压部件的安装位置预定的第一位置处配置由金属或合金构成的至少一个第一轨道，以及由金属或其合金构成的至少一个第二轨道 在沿着高电压部件的长度预定的第二位置处。 在一些实施例中，配置的至少一个第一轨道基本上减小了杂散电容效应，并且至少一个第二轨道沿着高压分量的长度产生基本线性的电压分布。

公开(公告)号：US07484293B2

公开(公告)日：2009-02-03

申请号：US11567804

申请日：2006-12-07

Applicant: Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

Inventor： Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

IPC: H05K3/34

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12. Vias 36 are arranged immediately above the bump terminals 16, and clearance holes 34, the diameter of which is smaller than the diameter of the bump terminals 16, are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

Abstract translation: 提供了具有优异的高频特性并且可以获得用于内部布线图案的大面积的半导体封装。 根据本发明，半导体封装包括：安装在多层布线板12的正面上的多层印刷布线板12和IC芯片以及安装在反面上的多个凸点端子16。 每个凸块端子16包括具有平坦面40的绝缘芯42和沉积在除了平面40之外的所有外表面上的导电涂层。导电涂层44的端面看起来像围绕绝缘芯42的环，并且是 焊接到形成在多层印刷电路板12的背面上的环形连接焊盘52.通孔36布置在凸块端子16的正上方，并且直径小于凸块端子16的直径的间隙孔34， 形成在内部布线图案28和30中以允许通孔36通过。

公开(公告)号：US07388158B2

公开(公告)日：2008-06-17

申请号：US10817785

申请日：2004-09-17

Applicant: Yeong Joo Yoon ,  Fernando Aguirre ,  Nicholas Teneketges

Inventor： Yeong Joo Yoon ,  Fernando Aguirre ,  Nicholas Teneketges

IPC: H01R12/04 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30

CPC classification number: H05K1/113 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0251 ,  H05K3/3436 ,  H05K2201/0792 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09809 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: In one embodiment, a substrate assembly includes a flat substrate having oppositely disposed planar surfaces and a conductor. The conductor is formed on at least one of the planar surfaces and defines a conductor plane. The structure further includes an oversized-in-diameter anti-pad formed through the substrate layer and the conductor layer. The anti-pad further includes a dielectric spacer formed substantially coplanar with the conductor plane.

Abstract translation: 在一个实施例中，衬底组件包括具有相对设置的平坦表面和导体的平坦衬底。 导体形成在至少一个平面表面上并且限定导体平面。 该结构还包括通过衬底层和导体层形成的超大直径的抗焊盘。 防焊盘还包括基本上与导体平面共面形成的电介质间隔物。

公开(公告)号：US07338290B2

公开(公告)日：2008-03-04

申请号：US11585959

申请日：2006-10-25

Applicant: Kenji Motohashi ,  Takashi Yanagimoto ,  Hideji Miyanishi ,  Kazumasa Aoki

Inventor： Kenji Motohashi ,  Takashi Yanagimoto ,  Hideji Miyanishi ,  Kazumasa Aoki

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H05K1/117 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A design rule for a printed wiring board is provided. A conductive layer and a pad are separate from each other in a distance defined by the design rule, which sufficiently prevents the capacitance coupling between the conductive layer and the pad.

Abstract translation: 提供印刷电路板的设计规则。 导电层和焊盘在由设计规则限定的距离内彼此分开，这足以防止导电层和焊盘之间的电容耦合。