公开(公告)号：US5999397A

公开(公告)日：1999-12-07

申请号：US958531

申请日：1997-10-27

申请人： Ming-Fa Chen ,  Shih-Shiung Chen ,  Ying-Chen Chao

发明人： Ming-Fa Chen ,  Shih-Shiung Chen ,  Ying-Chen Chao

IPC分类号： G03F7/20 ,  H05F1/00

CPC分类号： G03F1/66 ,  G03F7/70741 ,  H05F1/00

摘要： The present invention discloses a method for preventing electrostatic discharge damages to an article that is made of an insulating material and stored in a container also made of an insulating material by maintaining a minimum safe distance between the article and the top lid of the container such that a saturation electric field cannot be reached at such safety distance and thus electrostatic discharge does not occur. The present invention novel method can be utilized in carrying any insulating articles but is particularly suitable for carrying a quartz reticle in a polycarbonate pod.

摘要翻译： 本发明公开了一种防止对由绝缘材料制成的物品的静电放电损坏的方法，并且通过保持物品与容器顶盖之间的最小安全距离而将其储存在也由绝缘材料制成的容器中，使得 在这样的安全距离处不能达到饱和电场，因此不会发生静电放电。 本发明的新颖方法可用于承载任何绝缘制品，但特别适用于在聚碳酸酯荚中承载石英掩模版。

公开(公告)号：US10297550B2

公开(公告)日：2019-05-21

申请号：US12774558

申请日：2010-05-05

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC分类号： H01L23/538 ,  H01L23/488 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US08901736B2

公开(公告)日：2014-12-02

申请号：US12789696

申请日：2010-05-28

申请人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

发明人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L24/16 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/35 ,  Y10T428/12361 ,  Y10T428/12396 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

摘要： A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.

摘要翻译： 一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。 金属凸块和电介质层部分的表面形成界面。 在金属凸块上方形成金属涂层并与金属凸块接触。 金属表面从介电层上延伸到界面的下方。

公开(公告)号：US08820728B2

公开(公告)日：2014-09-02

申请号：US12617851

申请日：2009-11-13

申请人： Jao Sheng Huang ,  Ming-Fa Chen

发明人： Jao Sheng Huang ,  Ming-Fa Chen

IPC分类号： B23Q3/00

CPC分类号： H01L21/67346 ,  H01L21/67132

摘要： A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.

摘要翻译： 公开了一种用于保护半导体晶片的系统和方法。 优选实施例包括具有中心区域和外部区域的载体。 外部区域优选具有大于中心区域的厚度，以在载体中形成空腔。 优选将粘合剂放置在空腔中，并将半导体晶片放置在粘合剂上。 半导体晶片的边缘被凸起的外部区域以及至少部分地填充半导体晶片和载体的外部区域之间的区域的移位的粘合剂保护。

公开(公告)号：US08791549B2

公开(公告)日：2014-07-29

申请号：US12832019

申请日：2010-07-07

申请人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

发明人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

摘要翻译： 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US08546235B2

公开(公告)日：2013-10-01

申请号：US13101788

申请日：2011-05-05

申请人： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

发明人： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

IPC分类号： H01L21/20

CPC分类号： H01L28/40

摘要： An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.

摘要翻译： 集成电路包括衬底和设置在衬底上的第一金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器包括设置在基板上的第一金属电容器板。 至少一个第一绝缘体层设置在第一金属电容器板上。 第二金属电容器板设置在至少一个第一绝缘体层上。 至少一个第一电介质层设置在衬底上。 所述至少一个第一介电层的至少一部分设置在所述第一金属电容器板和所述至少一个第一绝缘体层之间。

公开(公告)号：US08362591B2

公开(公告)日：2013-01-29

申请号：US12795734

申请日：2010-06-08

申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

IPC分类号： H01L29/93

CPC分类号： H01L27/016 ,  H01L29/93

摘要： A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

摘要翻译： 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。

公开(公告)号：US08241963B2

公开(公告)日：2012-08-14

申请号：US12835189

申请日：2010-07-13

申请人： Wen-Wei Shen ,  Yao-Chun Chuang ,  Chen-Shien Chen ,  Ming-Fa Chen

发明人： Wen-Wei Shen ,  Yao-Chun Chuang ,  Chen-Shien Chen ,  Ming-Fa Chen

IPC分类号： H01L21/00

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13669 ,  H01L2224/13684 ,  H01L2224/16148 ,  H01L2224/81193 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01007 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00

摘要： A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

摘要翻译： 提供了可用于将一个衬底互连到另一衬底的凸块结构。 凹陷的导电柱形成在第一基板上，使得凹入的导电柱具有形成在其中的凹部。 凹部可以填充有焊料材料。 第二基板上的导电柱可以形成为具有宽度小于或等于凹部宽度的接触表面。 第一衬底可以附接到第二衬底，使得第二衬底上的导电柱位于第一衬底的凹部中或其中。 基板可以各自为集成电路管芯，插入件，印刷电路板，高密度互连等。

公开(公告)号：US20100224966A1

公开(公告)日：2010-09-09

申请号：US12683604

申请日：2010-01-07

申请人： Ming-Fa Chen

发明人： Ming-Fa Chen

IPC分类号： H01L23/48 ,  H01L23/498

CPC分类号： H01L24/10 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/522 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.

摘要翻译： 描述了用于半导体芯片的应力阻挡结构及其制造方法。 在一个实施例中，半导体器件包括半导体衬底，其包括有源电路和在有源电路上的互连金属化结构，其中互连金属化结构包括低k绝缘层的层。 第一金属凸块设置在半导体衬底上并耦合到半导体衬底的有源电路。 第一应力阻挡结构设置在金属凸块下方，并且设置在低k绝缘层上，并且第二基板设置在第一金属凸块的上方。

公开(公告)号：US5989754A

公开(公告)日：1999-11-23

申请号：US923980

申请日：1997-09-05

申请人： Shih-Shiung Chen ,  Ming-Fa Chen ,  Ho-Ku Lan ,  Ying-Chen Chao

发明人： Shih-Shiung Chen ,  Ming-Fa Chen ,  Ho-Ku Lan ,  Ying-Chen Chao

IPC分类号： G03F1/00 ,  G03F1/40 ,  G03F9/00

CPC分类号： G03F1/40

摘要： A photomask arrangement is disclosed to prevent the reticle patterns of a photomask from peeling caused by electrostatic discharge damage. The photomask includes: a substrate; a plurality of metal shielding layers formed on the surface of the substrate to provide the reticle patterns, wherein each two of the metal shielding layers are spaced apart by a clear scribe line; and a plurality of metal lines formed on the clear scribe line to connect the adjacent metal shielding layers, thereby increasing the effective surface area of the reticle patterns.

摘要翻译： 公开了一种光掩模布置，以防止光掩模的掩模版图案由静电放电损坏引起的剥离。 光掩模包括：基底; 形成在所述基板表面上的多个金属屏蔽层，以提供所述标线图案，其中每个所述金属屏蔽层通过清晰的划线间隔开; 以及形成在清晰划线上的多条金属线，以连接相邻的金属屏蔽层，从而增加标线图案的有效表面积。