公开(公告)号：US6093969A

公开(公告)日：2000-07-25

申请号：US313562

申请日：1999-05-15

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/24 ,  H01L23/495 ,  H01L25/10

CPC classification number: H01L23/24 ,  H01L23/4951 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/854 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

Abstract: The present invention discloses a face-to-face (FTF) stacked integrated circuit (IC) assembly. The FTF stacked IC assembly includes a first and a second substrate-on-bare-chip (SOBC) modules. Each of the first and second SOBC modules includes a printed circuit board (PCB) having a PCB bottom surface overlying an active circuit surface of a bare integrated circuit (IC) chip. The PCB includes a window opened substantially in a central portion of the active circuit surface of the bare IC chip. The bare IC chip includes bare-chip bonding-pads disposed on the active circuit surface in the window and the PCB includes a plurality of PCB bonding pads. Each of the first and second SOBC modules includes a plurality of bonding wires interconnecting the bare-chip bonding pads to the PCB bonding pads. Each of the first and second SOBC modules includes a plurality of solder balls disposed on a PCB top surface of the PCB connected to the PCB bonding pads with a plurality of metal traces disposed on the PCB board. The solder balls of first SOBC module mounted on the solder balls of the second SOBC module constituting a face-to-face (FTF) stacked SOBC assembly.

Abstract translation: 本发明公开了一种面对面（FTF）堆叠集成电路（IC）组件。 FTF堆叠IC组件包括第一和第二裸芯片（SOBC）模块。 第一和第二SOBC模块中的每一个包括印刷电路板（PCB），PCB印刷电路板底表面覆盖裸电路（IC）芯片的有源电路表面。 PCB包括基本上在裸IC芯片的有源电路表面的中心部分开口的窗口。 裸IC芯片包括设置在窗口中的有源电路表面上的裸芯片接合焊盘，并且PCB包括多个PCB焊盘。 第一和第二SOBC模块中的每一个包括将裸芯片接合焊盘互连到PCB焊盘的多个接合线。 第一和第二SOBC模块中的每一个包括多个焊球，其布置在PCB的PCB顶表面上，该PCB顶表面连接到具有设置在PCB板上的多个金属迹线的PCB焊盘。 安装在第二SOBC模块的焊球上的第一SOBC模块的焊球构成面对面（FTF）堆叠的SOBC组件。

公开(公告)号：US5468999A

公开(公告)日：1995-11-21

申请号：US249602

申请日：1994-05-26

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L23/24 ,  H01L23/31 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107

Abstract: A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

Abstract translation: 球栅阵列半导体器件（10）包括具有多个导电迹线（18），接合柱（20）和导电通孔（22）的封装衬底（14或16）。 半导体管芯（12）安装到封装衬底上。 正交线接合（28）用于将交错的接合焊盘（26）电连接到衬底上的对应的接合柱（20）。 液体密封剂（40）用于覆盖模具，引线键合和封装衬底的部分。 在另一个实施例中，封装衬底（50）包括下结合层（52）和上结合层（54）。 线接合（60）用于将外排的接合焊盘（64）电连接到下层（52）的接合柱（20），而引线接合（62）用于电连接内排接合焊盘 64）到上层（54）的粘合柱（20）。 引线键（60）的环路高度小于引线键合（62）。

公开(公告)号：US5378657A

公开(公告)日：1995-01-03

申请号：US205424

申请日：1994-03-04

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/10 ,  H01L23/495 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34 ,  H01L21/60

CPC classification number: H05K3/3426 ,  H01L21/4842 ,  H01L23/10 ,  H01L23/49534 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/30107 ,  H05K1/0271 ,  H05K2201/10689 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49121

Abstract: A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Abstract translation: 使用传统的包层和冲压技术制造用于CERQUAD的四引线框架（22'）。 第一金属层（12）设置有多个空腔（14）。 第二金属层（14）被包覆到第一金属层。 然后可以从复合金属冲压引线框条（22）。 引线框具有引线（24）和接合柱（28）。 引线包括两个金属层，并且接合柱仅包括第二金属层。 然后可以将引线框架用于半导体器件（32）的组装中。 可以任选地蚀刻包装体外部引线的部分以去除第二金属层。

公开(公告)号：US5329158A

公开(公告)日：1994-07-12

申请号：US964488

申请日：1992-10-21

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: C23C2/08 ,  C23C2/10 ,  C23C2/34 ,  H01L23/495 ,  H01L23/50 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC classification number: H01L23/49582 ,  H01L23/49579 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/10689 ,  H05K2201/10909 ,  H05K2201/10984 ,  H05K2201/2081 ,  Y02P70/613

Abstract: An improved semiconductor device is disclosed having a predetermined amount of solder, or other electrically conductive binder adsorbed onto the exterior package leads of the semiconductor device. A de-wettable coating comprising preferably nickel, or alternatively chromium, is plated to a superior portion of the package leads, such that, when the heat is applied to the substrate mounting end of the leads, solder desorbes from the de-wettable layer and flows down the lead to the contact pads on the mounting substrate and forms a solder joint. The amount of solder delivered to the contact pad for joint formation is determined by the thickness of the adsorbed solder layer overlying each package lead. Only enough solder is provided on each lead sufficient to form the joint thus avoiding solder bridging between adjacent contact pads.

Abstract translation: 公开了一种改进的半导体器件，其具有预定量的焊料或吸附到半导体器件的外部封装引线上的其它导电粘合剂。 包含优选镍或可选择的铬的脱湿涂层被电镀到封装引线的上部，使得当将热施加到引线的基板安装端时，来自脱湿层的焊料脱离和 沿着导线流到安装基板上的接触焊盘，并形成焊点。 输送到用于接合形成的接触焊盘的焊料的量由覆盖在每个封装引线上的吸附焊料层的厚度确定。 在每个引线上仅提供足够的焊料以形成接头，从而避免相邻接触焊盘之间的焊料桥接。

公开(公告)号：US5280193A

公开(公告)日：1994-01-18

申请号：US877930

申请日：1992-05-04

Applicant: Paul T. Lin ,  James W. Sloan

Inventor： Paul T. Lin ,  James W. Sloan

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/31 ,  H01L25/04 ,  H05K3/00 ,  H05K3/40 ,  H01L23/16 ,  H01L23/02 ,  H01L23/12 ,  H01L23/28

CPC classification number: H01L21/565 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/403

Abstract: A semiconductor multiple package module (10) on a PCB material substrate (18) is provided, wherein semiconductor dice are directly mounted onto the PCB material substrate (18) thereby eliminating a subsequent board mounting at the customer level. A plurality of semiconductor dice are mounted and electrically connected to a plurality of circuit traces (22) on the PCB material substrate (18) having a plurality of edge connectors (20). The plurality of circuit traces (22) has conductive paths to electrically interconnect the semiconductor dice to the edge connectors (20) and to each other. The semiconductor dice are directly overmolded on the PCB material substrate (18) with a molding compound to form individual semiconductor devices (12, 14, and 16) having separate package bodies. The individualized package bodies enable repair to the module by making removal of only nonfunctional semiconductor devices from the PCB material substrate (18) possible.

Abstract translation: 提供了一种在PCB材料基板（18）上的半导体多封装模块（10），其中将半导体晶片直接安装在PCB材料基板（18）上，从而消除了在客户层面上随后的板安装。 多个半导体晶片安装并电连接到具有多个边缘连接器（20）的PCB材料基板（18）上的多个电路迹线（22）。 多个电路迹线（22）具有导电路径，以将半导体晶片与边缘连接器（20）电互连并彼此连接。 半导体晶片通过模制化合物在PCB材料基板（18）上直接包覆成型，以形成具有单独封装体的单个半导体器件（12,14和16）。 通过从PCB材料基板（18）中仅去除非功能半导体器件，个性化的封装体能够修复模块。

公开(公告)号：US5273938A

公开(公告)日：1993-12-28

申请号：US876315

申请日：1992-04-30

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/498 ,  H05K3/34 ,  H01L21/28 ,  H01L21/60 ,  H01L21/70

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49855 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K3/3431 ,  Y10T29/49146

Abstract: A low cost manufacturing method is used to fabricate a small multichip semiconductor device (30). In one embodiment, a pattern of conductive traces (13) is formed on a film of transfer material (12). A first semiconductor die (15) is interconnected to the traces and a resin body (20) is formed around the first die and one side of the traces. The film of transfer material forms, at this stage of the process, one side of the first package. The film of transfer material is then peeled from the pattern of conductive traces and the first resin body to expose the other side of the traces. A second semiconductor die (23) is interconnected to the exposed side of the traces. A second resin body (25) is formed around the second die and portions of the exposed traces. Solder balls (26) are coupled to the exposed portions of the traces to establish external electrical connections to each die.

Abstract translation: 使用低成本制造方法来制造小型多芯片半导体器件（30）。 在一个实施例中，导电迹线（13）的图案形成在转印材料（12）的膜上。 第一半导体管芯（15）与迹线相互连接，树脂体（20）围绕第一管芯和迹线的一侧形成。 在该过程的这个阶段，转印材料的薄膜形成第一包装的一面。 然后将转印材料的膜从导电迹线图案和第一树脂体的图案剥离，以露出迹线的另一侧。 第二半导体管芯（23）与迹线的暴露侧相互连接。 第二树脂体（25）围绕第二管芯和暴露的迹线的一部分形成。 焊球（26）耦合到迹线的暴露部分以建立到每个管芯的外部电连接。

公开(公告)号：US5216278A

公开(公告)日：1993-06-01

申请号：US841765

申请日：1992-03-02

Applicant: Paul T. Lin ,  Michael B. McShane ,  Howard P. Wilson

Inventor： Paul T. Lin ,  Michael B. McShane ,  Howard P. Wilson

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/49827 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011

Abstract: A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

Abstract translation: 一种半导体器件（10），其具有通过形成在所述载体衬底（12）中的通孔（32）互连的载体衬底（12）的相对表面上的第一和第二布线层（30,33），所述通孔（32）将电子部件（18）电耦合到 通过从通孔（32）移开的柔性焊球（26）的安装基板，所述半导体器件（10）的特征在于具有高性能电气封装互连（24）和良好散热的标准尺寸的载体衬底（12）。 通过提供独立的布线层（30,33）来获得改善的电性能，每个独立布线层具有专门为特定的电子部件（18）设计的引线迹线布局和特定的板连接要求，同时使用标准尺寸封装轮廓。 通过在能够支撑本身具有不同尺寸的各种不同的电子部件（18）的标准尺寸的载体基板（12）上提供塑料封装模具（36）来减少装配成本。

公开(公告)号：US5045914A

公开(公告)日：1991-09-03

申请号：US663225

申请日：1991-03-01

Applicant: James J. Casto ,  Michael B. McShane ,  Paul T. Lin

Inventor： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/10 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49517 ,  H01L23/49589 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/09709 ,  H05K2201/10515 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H05K2201/10931 ,  H05K2201/2036 ,  H05K3/3426 ,  Y02P70/613

Abstract: A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure. The periphery of the package body may function as a carrier structure to protect the lead or connection structures during testing, handling and board mounting. The open vias permit back side testing of the device before or after mounting of the package to the PCB. Additionally, a heat sink structure and/or capacitor may be directly bonded to the side or the top of the pad array electronic device which may be used singly or in multiple, stacked configurations, to facilitate the thermal dissipation from the device.

Abstract translation: 用于安装在诸如印刷电路板（PCB）的基板上的焊盘阵列电子器件具有相对刚性的封装体，其具有多个孔，该多个孔承载用于结合到PCB上的焊盘的连接机构。 封装体可以是可以围绕电子部件注射模制的热固性塑料或其它材料，例如结合到引线框架的集成电路（IC）。 集成电路芯片或其他电子部件安装在引线框架附近或之上，并且通过任何常规方式制造集成电路芯片和框架之间的电连接。 在一个方面，衬底引线设置在其外端处，其被封装中的孔暴露以用于与PCB连接的焊球或焊盘。 封装体可以可选地用于从PCB离开设备一定距离，使得焊球将形成适当的凹形结构。 封装主体的周边可以用作载体结构，以在测试，处理和板安装期间保护引线或连接结构。 打开的通孔允许在将封装安装到PCB之前或之后对器件进行背面测试。 此外，散热器结构和/或电容器可以直接结合到可以单独使用或以多个堆叠配置使用的焊盘阵列电子器件的侧面或顶部，以便于从器件散热。

公开(公告)号：US5018005A

公开(公告)日：1991-05-21

申请号：US457648

申请日：1989-12-27

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L23/50 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30

CPC classification number: H01L22/00 ,  H01L23/3121 ,  H01L23/4985 ,  H05K3/303 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K2201/10303 ,  H05K2201/10681 ,  H05K2203/167 ,  Y02P70/613

Abstract: An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternate version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process. The periphery and test points may be sheared away before the package is mounted to the PCB. A variety of outer bonding area pitches may be provided on the same package with test points of a standard pitch. The relatively inexpensive device is thin and easily mounted by conventional techniques.

公开(公告)号：US4672421A

公开(公告)日：1987-06-09

申请号：US865572

申请日：1986-05-15

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/14 ,  H01L23/535 ,  H01L23/538 ,  H01L25/065 ,  H01L39/02

CPC classification number: H01L23/535 ,  H01L23/147 ,  H01L23/538 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19105

Abstract: A mounting means for a semiconductor integrated circuit, the mounting means comprising a semiconductor material having a mounting surface as one major surface thereof, a semiconductor integrated circuit mounted on the major surface of the semiconductor material, and means for electrically connecting the integrated circuit to the semiconductor material. The mounting means has a coefficient of thermal expansion similar to the semiconductor integrated circuit mounted thereon.

Abstract translation: 一种用于半导体集成电路的安装装置，所述安装装置包括具有作为其一个主表面的安装表面的半导体材料，安装在所述半导体材料的主表面上的半导体集成电路以及用于将所述集成电路电连接到所述半导体集成电路的装置 半导体材料。 安装装置具有类似于安装在其上的半导体集成电路的热膨胀系数。