公开(公告)号：US20160247785A1

公开(公告)日：2016-08-25

申请号：US15146811

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09299672B2

公开(公告)日：2016-03-29

申请号：US14280110

申请日：2014-05-16

Applicant: INTEL CORPORATION

Inventor： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

公开(公告)号：US10522454B2

公开(公告)日：2019-12-31

申请号：US15997555

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16 ,  H01L23/13

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

公开(公告)号：US20170084578A1

公开(公告)日：2017-03-23

申请号：US15367645

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Sven Albers ,  Michael Skinner ,  Hans-Joachim Barth ,  Peter Baumgartner ,  Harald Gossner

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/552 ,  H01L27/02 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564 ,  H01L23/66 ,  H01L24/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16105 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48482 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/85801 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.

公开(公告)号：US09601468B2

公开(公告)日：2017-03-21

申请号：US15146811

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01F7/04 ,  H01L25/065 ,  H01L23/32 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09368461B2

公开(公告)日：2016-06-14

申请号：US14280110

申请日：2014-05-16

Applicant: INTEL CORPORATION

Inventor： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/141 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0373

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract translation: 这里公开了与集成电路（IC）封装一起使用的接触焊盘。 在一些实施例中，本文公开的接触垫可以设置在IC封装的基板上，并且可以包括金属突出部分和金属凹部。 金属突出部和金属凹部中的每一个可以具有焊料接触表面。 金属凹部的焊接接触表面可以与金属突出部的焊接接触表面间隔开。 本文还公开了相关的设备和技术，并且可以要求保护其他实施例。

公开(公告)号：US20160148920A1

公开(公告)日：2016-05-26

申请号：US15009731

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

公开(公告)号：US11955462B2

公开(公告)日：2024-04-09

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US10128205B2

公开(公告)日：2018-11-13

申请号：US14199545

申请日：2014-03-06

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Sven Albers

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  G06F1/16 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/50

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.

公开(公告)号：US20170278778A1

公开(公告)日：2017-09-28

申请号：US15622552

申请日：2017-06-14

Applicant: INTEL CORPORATION

Inventor： Christian Geissler ,  Klaus Reingruber ,  Sven Albers

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49816 ,  H01L2924/15159 ,  H01L2924/15311

Abstract: An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate.