公开(公告)号：US20240283121A1

公开(公告)日：2024-08-22

申请号：US18436391

申请日：2024-02-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Yoko NAKABAYASHI ,  Noriyoshi SHIMIZU ,  Noritaka KATAGIRI ,  Tatsuki SUMI

IPC: H01P3/12 ,  H01P11/00

CPC classification number: H01P3/121 ,  H01P11/002

Abstract: A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.

公开(公告)号：US20220361340A1

公开(公告)日：2022-11-10

申请号：US17660701

申请日：2022-04-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi TANEDA ,  Noriyoshi SHIMIZU ,  Rie MIZUTANI ,  Masaya TAKIZAWA ,  Yoshiki AKIYAMA

IPC: H05K1/18 ,  H05K1/11

Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.

公开(公告)号：US20160353569A1

公开(公告)日：2016-12-01

申请号：US15158777

申请日：2016-05-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Jun FURUICHI ,  Noriyoshi SHIMIZU

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/0191 ,  H05K2201/0376 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2203/025

Abstract: A wiring substrate includes a core layer having a penetrating hole, a first insulating layer disposed on a first surface of the core layer and having a first opening at a position of the penetrating hole, the first insulating layer containing no filler, a penetrating electrode disposed in the penetrating hole and in the first opening, and a first wiring layer laminated both on the first insulating layer at a first surface thereof facing away from the core layer and on an end face of the penetrating electrode, wherein the first surface of the first insulating layer and the end face of the penetrating electrode are planarized.

Abstract translation: 布线基板包括具有穿透孔的芯层，设置在芯层的第一表面上的第一绝缘层，并且在穿透孔的位置处具有第一开口，第一绝缘层不包含填料，设置穿透电极 在所述贯通孔和所述第一开口中的第一表面以及在所述第一绝缘层上层叠的第一布线层，所述第一布线层在其背离所述芯层的第一表面和所述穿透电极的端面上， 绝缘层和穿透电极的端面被平坦化。

公开(公告)号：US20150357276A1

公开(公告)日：2015-12-10

申请号：US14730743

申请日：2015-06-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Kiyoshi OI ,  Yuichiro SHIMIZU

IPC: H01L23/498 ,  H05K3/00 ,  H05K1/09 ,  H05K1/18 ,  H01L21/48 ,  H05K1/03

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/181 ,  H05K3/0023 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2203/061 ,  Y10T29/49167 ,  H01L2924/00

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.

Abstract translation: 布线基板包括堆叠在其上的第一布线结构和第二布线结构。 第一布线结构包括延伸穿过第一绝缘层的第一绝缘层和通孔布线。 第二布线结构包括形成在第一绝缘层和通孔布线上的第一布线层和堆叠在第一绝缘层上并且在平面图中至少部分网格形状以限定第二通孔的第一平面层。 第二绝缘层堆叠在第一绝缘层上以填充第二通孔并覆盖第一平面层和第一布线层。 第二布线结构具有比第一布线结构更高的布线密度。 第二通孔各自包括下开口端和具有比下开口端小的开口宽度的上开口端。

公开(公告)号：US20150305153A1

公开(公告)日：2015-10-22

申请号：US14675819

申请日：2015-04-01

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kei IMAFUJI ,  Noriyoshi SHIMIZU ,  Kiyoshi OI ,  Hiromu ARISAKA

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K3/4007 ,  H01L2224/11 ,  H05K1/0298 ,  H05K3/244 ,  H05K3/3436

Abstract: A wiring substrate includes an insulating layer, and a connection terminal formed on the insulating layer. The connection terminal includes a metal layer formed on the insulating layer and including an upper surface, a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and a surface plating layer that covers the upper and side surfaces of the metal post. The metal layer includes a material that is inactive with respect to a material included in the surface plating layer. The metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view. The surface plating layer is formed to expose the upper surface edge part of the metal layer.

Abstract translation: 布线基板包括绝缘层和形成在绝缘层上的连接端子。 连接端子包括形成在绝缘层上并包括上表面的金属层，形成在金属层的上表面上并包括上表面和侧表面的金属柱，以及覆盖上表面和侧表面的表面镀层 金属柱。 金属层包括相对于包含在表面镀层中的材料是无活性的材料。 金属层具有在平面图中从金属柱的侧表面暴露在外部的上表面边缘部分。 形成表面镀层以露出金属层的上表面边缘部分。

公开(公告)号：US20130328211A1

公开(公告)日：2013-12-12

申请号：US13910325

申请日：2013-06-05

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Akio ROKUGAWA ,  Akihiko TATEIWA ,  Masato TANAKA

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/81193 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a semiconductor chip, a core substrate, first and second insulating layers, and first and second wiring layers. Adhesiveness of the insulating layer to a metal is higher than adhesiveness of the core substrate to the metal. A through hole extends through the insulating layer in the thickness direction. A through via covers the hole wall surface of the through hole, extends in the thickness direction traversing the insulating layer, and electrically connects the first and second wiring layers.

Abstract translation: 半导体器件包括半导体芯片，芯基板，第一和第二绝缘层以及第一和第二布线层。 绝缘层对金属的粘附性高于芯基板与金属的粘合性。 通孔在厚度方向上延伸穿过绝缘层。 通孔覆盖通孔的孔壁表面，沿着穿过绝缘层的厚度方向延伸，并且电连接第一和第二布线层。

公开(公告)号：US20160020163A1

公开(公告)日：2016-01-21

申请号：US14791670

申请日：2015-07-06

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Jun FURUICHI ,  Akio ROKUGAWA ,  Takashi Ito

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/095 ,  H05K1/111 ,  H05K1/112 ,  H05K1/114 ,  H05K1/115 ,  H05K3/0073 ,  H05K3/383 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/0392 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

Abstract translation: 布线基板包括第一布线结构和第二布线结构。 第一布线结构包括覆盖第一布线层的第一绝缘层和通孔布线。 第一绝缘层的第一通孔填充有通孔布线。 第二布线结构包括第二布线层和第二绝缘层。 第二布线层形成在第一绝缘层的上表面和通孔布线的上端面上。 第二布线层部分地包括粗糙表面。 第二绝缘层堆叠在第一绝缘层的上表面上并覆盖第二布线层。 第二布线结构具有比第一布线结构更高的布线密度。 第二布线层的粗糙化表面的表面粗糙度比第一布线层小。

公开(公告)号：US20150282307A1

公开(公告)日：2015-10-01

申请号：US14613591

申请日：2015-02-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Shoji WATANABE ,  Toshinori KOYAMA ,  Akio ROKUGAWA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K3/4682 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/10156 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13666 ,  H01L2224/13687 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H05K1/111 ,  H05K1/115 ,  H05K2201/0352 ,  H05K2203/025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/04941

Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.

Abstract translation: 布线板包括第一绝缘层; 第一布线层; 首先通过布线; 第二绝缘层; 第二布线层; 第二条通过布线; 以及阻焊层，其中，所述第一绝缘层由非感光性树脂构成，所述第二绝缘层和所述阻焊层分别由感光性树脂构成，其中，所述第一绝缘层和所述第二绝缘层的第一表面 嵌入在最上面的第一绝缘层中的第一通孔布线的第一端面是抛光表面，其中嵌入在最上面的第一绝缘层中的第一通孔布线的第一端面与最上面的第一绝缘层的第一表面齐平， 其中所述第二布线层的布线密度高于所述第一布线层的布线密度。

公开(公告)号：US20150179560A1

公开(公告)日：2015-06-25

申请号：US14548784

申请日：2014-11-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiromu Arisaka ,  Noriyoshi SHIMIZU ,  Masato TANAKA ,  Tetsuya KOYAMA ,  Akio ROKUGAWA

IPC: H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K1/02 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/0366 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/0137 ,  H05K2201/029 ,  H05K2201/0296 ,  H01L2924/00

Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.

Abstract translation: 布线基板包括第一和第二布线结构。 第一布线结构包括芯基板，由包括增强材料的热固性绝缘树脂形成的第一绝缘层和第二绝缘层，以及形成在第一绝缘层中的通孔布线。 第二布线结构包括形成在第一绝缘层和通孔导线的上表面上的布线层，形成在第一绝缘层的上表面上的绝缘层，以及包括用于将半导体 芯片和布线层。 堆叠在第二绝缘层的下表面上的最外绝缘层暴露作为外部连接焊盘堆叠在第二绝缘层的下表面上的最下布线层的一部分。 第二布线结构具有比第一布线结构更高的布线密度。

公开(公告)号：US20150163899A1

公开(公告)日：2015-06-11

申请号：US14625757

申请日：2015-02-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Hitoshi SAKAGUCHI ,  Wataru KANEDA ,  Masato TANAKA ,  Akio ROKUGAWA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0298 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/181 ,  H05K3/4007 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/025 ,  H01L2924/00

Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.

Abstract translation: 布线板依次包括在芯层上形成的第一绝缘层和第二绝缘层; 依次形成在芯层的另一表面上的第三绝缘层和阻焊层，分别形成在第一绝缘层和第二绝缘层中的第一布线层和第二布线层，其中第一绝缘层和第一绝缘层的第一端面 通过布线从最外侧的第一绝缘层的第一表面暴露出来，与最外层的第二布线层直接连接，第一通孔布线和最外层的第二布线层被分开地形成，最外面的第一绝缘层的第一表面和第一 第一通孔布线的端面是抛光表面，光滑的表面并且彼此齐平，并且第二布线层的布线密度高于第一布线层的布线密度。