公开(公告)号：US09076881B2

公开(公告)日：2015-07-07

申请号：US14171048

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/13075 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract translation: 提供一种凸块结构，包括第一凸块和第二凸块，包括该凸块的半导体封装及其制造方法。 凸块结构包括：设置在基板的连接焊盘上的第一凸块，所述第一凸块包括从所述连接焊盘延伸的多个纳米线和连接所述多个纳米线的端部的主体; 以及设置在第一凸块的主体上的第二凸块。

公开(公告)号：US11018026B2

公开(公告)日：2021-05-25

申请号：US16699283

申请日：2019-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H05K1/11 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14

Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.

公开(公告)号：US10134702B2

公开(公告)日：2018-11-20

申请号：US15494942

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Cha-jea Jo ,  Tae-Je Cho

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US09875918B2

公开(公告)日：2018-01-23

申请号：US14788783

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Dong Jung ,  Jung-Hwan Kim ,  Dong-Gil Lee ,  Tae-Je Cho ,  Kwang-Chul Choi

IPC: B32B43/00 ,  H01L21/67 ,  B32B38/10 ,  B32B41/00

CPC classification number: H01L21/67115 ,  B32B38/10 ,  B32B41/00 ,  B32B43/006 ,  B32B2250/02 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L21/67092 ,  H01L21/67253 ,  H01L2221/68381 ,  H01L2224/98 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

公开(公告)号：US09287140B2

公开(公告)日：2016-03-15

申请号：US14264123

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Jongyeon Kim ,  In-Young Lee ,  Tae-Je Cho

IPC: H01L21/00 ,  H01L21/48 ,  H01L25/00 ,  H01L21/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

Abstract translation: 提供了具有通孔的半导体封装及其制造方法。 该方法可以包括形成包括层叠在第二半导体芯片上的第一半导体芯片的晶片级封装，形成芯片级封装，芯片级封装包括堆叠在堆叠多个芯片级封装上的第三半导体芯片上的第四半导体芯片 晶片级封装的第二半导体衬底的后表面，抛光晶片级封装的第一模具层和第一半导体芯片，以暴露第一半导体芯片的第一贯穿电极，并在第一半导体芯片上形成外部电极 半导体芯片分别连接到第一贯通电极。

公开(公告)号：US09165916B2

公开(公告)日：2015-10-20

申请号：US14326631

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyunsoo Chung ,  Seungduk Baek ,  In-Young Lee ,  Tae-Je Cho

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package and a method of fabricating the same. The method may include mounting a lower stack including a plurality of lower semiconductor chips on a substrate and mounting an upper stack including a plurality of upper semiconductor chips on the lower stack. According to example embodiments of the inventive concept, the semiconductor package can be easily fabricated.

Abstract translation: 一种半导体封装及其制造方法。 该方法可以包括将包括多个下半导体芯片的下堆叠安装在基板上，并且在下堆叠上安装包括多个上半导体芯片的上堆叠。 根据本发明构思的示例实施例，可以容易地制造半导体封装。

公开(公告)号：US09853012B2

公开(公告)日：2017-12-26

申请号：US15010438

申请日：2016-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Jongyeon Kim ,  In-Young Lee ,  Tae-Je Cho

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L21/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/03 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

公开(公告)号：US20170125387A1

公开(公告)日：2017-05-04

申请号：US15402521

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： UN-BYOUNG KANG ,  Tae-Je Cho ,  Byung-Hyug Roh

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1413 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1713 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

公开(公告)号：US09324683B2

公开(公告)日：2016-04-26

申请号：US14318643

申请日：2014-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hong Min ,  Young-Kun Jee ,  Tae-Je Cho

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/433 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/2732 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/92225 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/07802

Abstract: In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability.

Abstract translation: 在一个实施例中，半导体封装包括电路基板，堆叠在电路基板上的多个半导体芯片，插入在半导体芯片之间的绝缘粘合剂图案，设置在最上半导体芯片上的散热片，并通过 散热粘合剂图案，以及设置在电路基板上以覆盖半导体芯片的侧壁，绝缘粘合剂图案，散热粘合剂图案和热块的模具结构。 在模具结构的制造过程中半导体封装的故障可能会降低。 因此，半导体封装可具有良好的工作特性和可靠性。

公开(公告)号：US08980689B2

公开(公告)日：2015-03-17

申请号：US14088576

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo Kwak ,  Cha-Jea Jo ,  Tae-Je Cho ,  Sang-Uk Han

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract translation: 提供一种制造多芯片堆叠封装的方法。 该方法包括制备具有单体下部芯片衬底的单体下部芯片，其具有第一表面和与第一表面相对设置的第二表面，将单元封装衬底粘合到单体下部芯片衬底的第一表面上以形成 单体衬底芯片接合结构，将单体衬底 - 芯片接合结构分离成多个单元衬底 - 芯片接合结构，制备具有单体上片状衬底的单体上片，将多个单元 衬底 - 芯片接合结构到单体上芯片衬底的第一表面上以形成单体半导体芯片堆叠结构，并将单体半导体芯片堆叠结构分离成多个单元半导体芯片堆栈结构。