公开(公告)号：US20130191567A1

公开(公告)日：2013-07-25

申请号：US13793719

申请日：2013-03-11

Applicant: Broadcom Corporation

Inventor： Ahmadreza ROFOUGARAN ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC: G06F13/42

CPC classification number: G06F9/50 ,  H04B5/0037 ,  H04B7/10 ,  H04B7/26 ,  H04W4/80 ,  H04W84/18 ,  Y10T307/492

Abstract: Embodiments of the present invention are directed to a wire-free data center/server. The data center/server is wire-free in the sense that communication within a data unit of the data center/server (i.e., intra-data unit), between data units of the data center/server (inter-data unit), and between the data units and the backplane of the data center/server is performed wirelessly.

Abstract translation: 本发明的实施例涉及一种无线数据中心/服务器。 在数据中心/服务器（数据单元）的数据单元之间，数据中心/服务器（数据间单元）的数据单元和数据中心/服务器的数据单元（即，数据内单元）内的通信和数据中心/服务器 在数据单元和数据中心/服务器的背板之间进行无线通信。

公开(公告)号：US09431370B2

公开(公告)日：2016-08-30

申请号：US14147237

申请日：2014-01-03

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014

Abstract: Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

Abstract translation: 为半导体器件和集成电路（IC）封装提供的系统，装置和方法，其包括兼容的电介质层。 在通过硅通孔插入器或衬底中，柔性介电材料可以被添加到硅材料体的表面以形成柔顺的介电层。 柔性电介质层为所得IC封装提供热缓冲器和应力缓冲器。 柔性介电材料可以被选择成使得柔性介电材料的热膨胀系数近似匹配安装有IC封装的电路板的热膨胀系数。 可以选择兼容的介电材料，使得其具有大于硅材料体的可变形性。 可以使用多个顺应介电材料的子层。

公开(公告)号：US09219054B2

公开(公告)日：2015-12-22

申请号：US14147237

申请日：2014-01-03

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

Abstract: Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

公开(公告)号：US20150276856A1

公开(公告)日：2015-10-01

申请号：US14735994

申请日：2015-06-10

Applicant: Broadcom Corporation

Inventor： Jesus Alfonso Castaneda ,  Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Michael Boers

IPC: G01R31/28 ,  G01R31/303 ,  G01R31/302

CPC classification number: G01R31/2834 ,  G01R31/2822 ,  G01R31/2831 ,  G01R31/3025 ,  G01R31/303 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Abstract translation: 公开了用于在集成电路内的集成电路和/或功能模块之间进行无线通信的方法和装置。 半导体器件制造操作使用预定的照相和/或化学处理步骤顺序在半导体衬底上形成一个或多个功能模块。 功能模块耦合到形成在半导体衬底上和/或连接到其上以形成集成电路的集成波导。 功能模块通过集成波导使用多址传输方案彼此通信以及其他集成电路。 一个或多个集成电路可以耦合到集成电路载体以形成多芯片模块。 多芯片模块可以耦合到半导体封装以形成封装的集成电路。

公开(公告)号：US20150223275A1

公开(公告)日：2015-08-06

申请号：US14615866

申请日：2015-02-06

Applicant: Broadcom Corporation

Inventor： Ahmadreza (Reza) ROFOUGARAN ,  Arya Reza Behzad ,  Michael Boers ,  Jesus Alfonso Castaneda ,  Sam Ziqun Zhao

IPC: H04W76/02 ,  H04B7/26

CPC classification number: G06F9/50 ,  H04B5/0037 ,  H04B7/10 ,  H04B7/26 ,  H04W4/80 ,  H04W84/18 ,  Y10T307/492

Abstract: Disclosed herein are systems, apparatuses, and methods for creating a system of wireless-enabled components (WECs). Such a system includes a server and a plurality of wireless-enabled component (WECs). Each WEC includes a functional resource (e.g., a processing resource and/or a memory resource) and is configured for wireless communication with the server and one or more other WECs. A first WEC is configured to wirelessly upload, to the server, an availability of the functional resource of the first WEC. The first WEC is further configured to wirelessly download, from the server, a linking resource for linking with one or more of the plurality of WECs. The plurality of WECs may be located on a single chip, on multiple chips of a single device, or on multiple chips of multiple devices.

Abstract translation: 这里公开了用于创建无线组件（WEC）的系统的系统，设备和方法。 这样的系统包括服务器和多个无线使能分量（WEC）。 每个WEC包括功能资源（例如，处理资源和/或存储器资源），并且被配置用于与服务器和一个或多个其他WEC的无线通信。 第一WEC被配置为向服务器无线地上传第一WEC的功能资源的可用性。 第一WEC还被配置为从服务器无线地下载链接资源，用于与多个WEC中的一个或多个相关联。 多个WEC可以位于单个芯片上，在单个设备的多个芯片上，或者位于多个设备的多个芯片上。

公开(公告)号：US09406793B2

公开(公告)日：2016-08-02

申请号：US14529959

申请日：2014-10-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Frank Hui

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7809 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/7827

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract translation: 半导体器件和制造方法被提供用于使通道和栅极长度独立于光刻。 此外，提供半导体器件和制造方法用于增加漏极和沟道之间的电阻率，以允许更高的电压操作。 例如，半导体器件包括注入形成源极或漏极之一的半导体衬底中的第一掺杂层和设置在第一掺杂层上的栅极金属层。 半导体器件还包括设置在形成另一个源极或漏极的栅极金属上的第二掺杂层，其中第一掺杂层，栅极金属层和第二掺杂层形成半导体器件的垂直堆叠层。 所述半导体器件还包括形成在沟槽中的导电沟道，所述沟槽垂直延伸穿过所述垂直堆叠层并终止于所述半导体衬底。

公开(公告)号：US09406636B2

公开(公告)日：2016-08-02

申请号：US14715484

申请日：2015-05-18

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/30131 ,  H01L2224/30141 ,  H01L2224/30179 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

公开(公告)号：US09390993B2

公开(公告)日：2016-07-12

申请号：US14518947

申请日：2014-10-20

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Galen Kirkpatrick ,  Edward Law ,  Reza Khan ,  Ming Wang Sze

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L23/3178 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/544 ,  H01L24/14 ,  H01L24/46 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface.

Abstract translation: 半导体封装包括包含有源电路层的半导体单元。 半导体封装还包括有源电路层上的多个接合焊盘，其被配置为连接到对应的外部导电连接器。 半导体封装还包括填充有源电路层的沟槽边缘的保护性密封剂涂层。 保护性密封剂涂层包含外部晶片单面。

公开(公告)号：US09293393B2

公开(公告)日：2016-03-22

申请号：US14175985

申请日：2014-02-07

Applicant: BROADCOM CORPORATION

Inventor： Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Sampath K. V. Karikalan ,  Xiangdong Chen

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/50

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/78 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Abstract translation: 本公开的示例性实施方案包括具有来自位于底部重构晶片的底模上方的顶部重构晶片的顶模的堆叠封装。 顶部模具和底部模具通过绝缘装置彼此绝缘。 顶模和底模也通过绝缘装置互连。 绝缘装置可以包括在顶模侧面的顶部模塑料和位于底模侧面的底部模塑料。 顶部模具和底部模具可以通过至少顶部模塑料相互连接。 此外，顶模和底模可以通过在绝缘装置内延伸的导电通孔相互连接。

公开(公告)号：US20140367854A1

公开(公告)日：2014-12-18

申请号：US13927470

申请日：2013-06-26

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/00

CPC classification number: H01L23/49833 ,  H01L23/3142 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4046 ,  H05K3/4688 ,  H05K2201/0218 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/041 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012

Abstract: Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate.

Abstract translation: 为模制IC封装的互连结构提供了各种实例。 在一个示例中，其中，IC封装包括基板和插入件。 多个导电元件在基板的表面和插入件的表面之间提供物理和电接触。 设置在基板和插入件的表面之间的间隔元件在基板和插入件的表面之间提供最小的间隔。 在一些实施方案中，支架元件设置在设置在基板的表面上的IC管芯和插入件的表面之间。 在另一示例中，一种方法包括将导电元件耦合到插入件的表面，附接支架元件，将导电元件耦合到基板的表面，以及在插入器和基板之间形成嵌入层。 支座元件限定了插入件和基板之间的最小间隙。