公开(公告)号：US20070222065A1

公开(公告)日：2007-09-27

申请号：US11385121

申请日：2006-03-21

Applicant: Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

Inventor： Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

IPC: H01L21/00 ,  H01L23/34

CPC classification number: H01L24/81 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/81001 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/20109 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Abstract translation: 一种电子潜水及其制造方法。 所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准 集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

公开(公告)号：US20070099342A1

公开(公告)日：2007-05-03

申请号：US11566956

申请日：2006-12-05

Applicant: John Knickerbocker ,  Voya Markovich ,  Thomas Miller ,  William Rudik

Inventor： John Knickerbocker ,  Voya Markovich ,  Thomas Miller ,  William Rudik

IPC: H01L21/00

CPC classification number: H05K1/0271 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/384 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/1152 ,  H01L2924/00

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Abstract translation: 提供了具有降低的BGA焊盘与层压体表面的粘附性的球栅阵列封装及其制造方法。

公开(公告)号：US20050110160A1

公开(公告)日：2005-05-26

申请号：US10721984

申请日：2003-11-25

Applicant: Mukta Faroog ,  John Knickerbocker ,  Frank Pompeo ,  Subhash Shinde

Inventor： Mukta Faroog ,  John Knickerbocker ,  Frank Pompeo ,  Subhash Shinde

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/36 ,  H01L23/49827 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/16195

Abstract: Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

Abstract translation: 在本发明中，半导体芯片通过插入件结构与基板（例如有机，陶瓷等）电连接。 插入器结构包括弹性体柔性材料，其包括具有预定形状的通过连接的冶金。 在典型的实施例中，冶金通孔连接将半导体芯片的凸起下金属化电连接到衬底的顶表面金属化。 通过利用根据本发明的插入器结构，可以减轻与先前的半导体模块设计相关的问题。

公开(公告)号：US20110290406A1

公开(公告)日：2011-12-01

申请号：US12788843

申请日：2010-05-27

Applicant: Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

Inventor： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC: B29C65/16

CPC classification number: H01L21/6835 ,  B23K26/361 ,  H01L2221/68381 ,  Y10T156/1111 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

Abstract translation: 一种用于从晶片释放处理器的方法，包括集成电路（IC）的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。 一种用于从晶片释放处理器的系统，包括IC的晶片包括使用包含聚合物的粘合剂连接到晶片的处理器; 边缘处理模块，所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器，激光器被配置为通过处理器消融粘合剂。

公开(公告)号：US20080206960A1

公开(公告)日：2008-08-28

申请号：US11679226

申请日：2007-02-27

Applicant: Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

Inventor： Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

IPC: H01L21/30

CPC classification number: G01R31/2898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point.

Abstract translation: 一种用于从衬底去除薄化硅结构的方法，所述方法包括用焊接连接选择硅结构以便去除; 将硅结构去除装置施加到所述硅结构和所述衬底，其中所述硅结构去除装置包括用于在所述焊接连接的熔点的约80％到约熔点范围内的致动的预定温度设定点; 将硅结构去除装置和硅结构的焊接连接加热到致动硅结构去除装置的范围内; 并去除薄的硅结构。 还公开了包括多个层的结构，至少一个层，包括薄化硅结构和将该层耦合到多个层中的另一层的焊料; 其中每层的焊料具有预定的熔点。

公开(公告)号：US20080000080A1

公开(公告)日：2008-01-03

申请号：US11856084

申请日：2007-09-17

Applicant: William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

Inventor： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

IPC: H05K3/00

CPC classification number: H01L24/13 ,  G01R1/06716 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L2221/68377 ,  H01L2224/11003 ,  H01L2224/114 ,  H01L2224/11505 ,  H01L2224/116 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/06 ,  H05K3/3436 ,  H05K2201/10242 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

Abstract translation: 形成顺应性电触头的方法包括将导电层图案化为顺应构件阵列。 然后将顺应构件阵列定位成与集成电路晶片上的电连接焊盘接触，并且柔性构件连接到焊盘。 然后，移除支撑柔顺构件的支撑层，以使与柔性构件连接的衬垫离开。

公开(公告)号：US20070246515A1

公开(公告)日：2007-10-25

申请号：US11409232

申请日：2006-04-21

Applicant: Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

Inventor： Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

IPC: B23K31/02 ,  B23K1/08 ,  B23K35/12

CPC classification number: B23K3/0638 ,  B23K35/02 ,  B23K2101/40 ,  H01L2224/11

Abstract: A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head.

Abstract translation: 公开了一种用于将导电接合材料注射成非矩形模具中的多个空腔的系统和方法。 该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被放置成与非矩形模具基本接触。 旋转运动提供给非矩形模具和填充头中的至少一个，同时填充头基本上与非矩形模具接触。 将导电接合材料从填充头推向非矩形模具。 导电接合材料被提供到与填充头附近的至少一个空腔同时的多个空腔的至少一个空腔中。

公开(公告)号：US20070035030A1

公开(公告)日：2007-02-15

申请号：US11201572

申请日：2005-08-11

Applicant: Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

Inventor： Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20060211167A1

公开(公告)日：2006-09-21

申请号：US10907062

申请日：2005-03-18

Applicant: John Knickerbocker ,  Hai Longworth ,  Roger Quon

Inventor： John Knickerbocker ,  Hai Longworth ,  Roger Quon

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L24/10 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01059 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00

Abstract: Disclosed are microelectronic structures based on improved design and material combinations to provide improved current capabilities per I/O. The preferred embodiment of the invention uses a combination of one or more of the following: (1) Underbump metallurgy which enhances current per I/O by increasing via diameter or by having multiple via openings under BLM; (2) Thicker underbump metallurgy, where use of good conductor metallurgies can be used with increased thickness; (3) Utilizing larger via diameter under bump metallurgy, larger solder bump diameter and/or other current enhancing features for power and/or ground via connections; and (4) Using additives in Pb-free alloys to alter microstructure to minimize migration of atoms in the solder or at intermetallic transitions.

Abstract translation: 公开了基于改进的设计和材料组合的微电子结构，以提供每I / O改进的电流能力。 本发明的优选实施例使用以下一种或多种的组合：（1）通过增加通孔直径或通过在BLM下具有多个通孔而增加每I / O电流的底部焊接冶金; （2）较厚的底部焊接冶金，使用良好的导体冶金可以增加厚度; （3）使用较大的通孔直径凸块下冶金，较大的焊料凸块直径和/或其他电流增强特征用于通过连接的电源和/或接地; 和（4）使用无铅合金中的添加剂来改变微结构以最小化焊料中原子或金属间跃迁的迁移。

公开(公告)号：US20060177568A1

公开(公告)日：2006-08-10

申请号：US11049846

申请日：2005-02-04

Applicant: Gareth Hougham ,  Leena Buchwalter ,  Stephen Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey Gelorme ,  Kathleen Hinge ,  Anurag Jain ,  Sung Kang ,  John Knickerbocker

Inventor： Gareth Hougham ,  Leena Buchwalter ,  Stephen Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey Gelorme ,  Kathleen Hinge ,  Anurag Jain ,  Sung Kang ,  John Knickerbocker

IPC: B05D5/12 ,  H05K3/00 ,  B05C1/00

CPC classification number: H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract translation: 本公开一般涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，糊料，材料悬浮液，用作导电，结构 支撑或电子部件的保护构件。