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    Semiconductor devices with underfill control features, and associated systems and methods
    21.
    发明授权
    Semiconductor devices with underfill control features, and associated systems and methods 有权

    公开(公告)号：US10424553B2

    公开(公告)日：2019-09-24

    申请号：US15339693

    申请日：2016-10-31

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Yeruva ,  Kyle K. Kirby ,  Owen R. Fay ,  Sameer S. Vadhavkar

    IPC: H01L23/00 ,  H01L23/24 ,  H01L21/56 ,  H01L23/31

    Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.

    Package-on-package semiconductor assemblies and methods of manufacturing the same
    22.
    发明授权
    Package-on-package semiconductor assemblies and methods of manufacturing the same 有权

    公开(公告)号：US10381297B2

    公开(公告)日：2019-08-13

    申请号：US16027041

    申请日：2018-07-03

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    Package-on-package semiconductor assemblies and methods of manufacturing the same
    23.
    发明授权
    Package-on-package semiconductor assemblies and methods of manufacturing the same 有权

    公开(公告)号：US10032703B2

    公开(公告)日：2018-07-24

    申请号：US15229668

    申请日：2016-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Jack E. Murray

    IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    STACKED INTERPOSER STRUCTURES, AND RELATED METHODS
    28.
    发明申请
    STACKED INTERPOSER STRUCTURES, AND RELATED METHODS 有权

    公开(公告)号：US20250149530A1

    公开(公告)日：2025-05-08

    申请号：US19019138

    申请日：2025-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16

    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

    NON-CONDUCTIVE FILM FILLET CONTROL IN SEMICONDUCTOR DEVICE ASSEMBLY
    29.
    发明申请
    NON-CONDUCTIVE FILM FILLET CONTROL IN SEMICONDUCTOR DEVICE ASSEMBLY 有权

    公开(公告)号：US20250132279A1

    公开(公告)日：2025-04-24

    申请号：US18790320

    申请日：2024-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay

    IPC: H01L23/00

    Abstract: A semiconductor device is presented. The semiconductor device includes a lower semiconductor die, a stack of upper semiconductor dies disposed over the lower semiconductor die, a non-conductive film material disposed between adjacent semiconductor dies of the lower semiconductor die and the stack of upper semiconductor dies, and an epoxy material disposed on at least one sidewall of the stack of upper semiconductor dies, wherein the epoxy material has a different material composition to the NCF material.

    LOW COST THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES
    30.
    发明申请
    LOW COST THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES 有权

    公开(公告)号：US20240371755A1

    公开(公告)日：2024-11-07

    申请号：US18774763

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L25/065 ,  H01M50/414 ,  H05K9/00

    Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.

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