公开(公告)号：US11387245B2

公开(公告)日：2022-07-12

申请号：US16851638

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. McKinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11556

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

公开(公告)号：US20210343624A1

公开(公告)日：2021-11-04

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/033 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US20210225715A1

公开(公告)日：2021-07-22

申请号：US17207989

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Lisa R. Copenspire-Ross ,  Michael D. Kenney

IPC: H01L21/66 ,  G01N21/95 ,  H01L23/00

Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.

公开(公告)号：US20210202515A1

公开(公告)日：2021-07-01

申请号：US16728723

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  S.M. Istiaque Hossain ,  Darwin A. Clampitt ,  Arun Kumar Dhayalan ,  Kevin R. Gast ,  Christopher Larsen ,  Prakash Rau Mokhna Rau ,  Shashank Saraf

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b). At least one horizontally-elongated isolation structure is formed in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions. Additional methods, including structure independent of method, are disclosed.

公开(公告)号：US10957625B2

公开(公告)日：2021-03-23

申请号：US15858501

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

公开(公告)号：US10461061B2

公开(公告)日：2019-10-29

申请号：US16272190

申请日：2019-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

公开(公告)号：US20170352633A1

公开(公告)日：2017-12-07

申请号：US15684054

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02135 ,  H01L2224/02166 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05566 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/049 ,  H01L2924/06 ,  H01L2924/04953

Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

公开(公告)号：US09397078B1

公开(公告)日：2016-07-19

申请号：US14635888

申请日：2015-03-02

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/563 ,  H01L23/04 ,  H01L23/367 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16235 ,  H01L2924/00

Abstract: Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first semiconductor die having a base region formed from a substrate material, a recessed surface along the base region, a peripheral region formed from the substrate material and projecting from the base region, and a sidewall surface along the peripheral region and defining a cavity with the sidewall surface in the peripheral region. The semiconductor device assembly further includes a thermal transfer structure attached to the peripheral region of the first die adjacent the cavity, and an underfill material at least partially filling the cavity and including a fillet between the peripheral region and the stack of second semiconductor dies.

Abstract translation: 本文公开了具有底部填充容纳腔的半导体器件组件。 在一个实施例中，半导体器件组件可以包括第一半导体管芯，其具有由基底材料形成的基极区域，沿着基底区域的凹陷表面，由基底材料形成并从底部区域突出的外围区域，以及侧壁 沿着周边区域形成表面，并且在周边区域中限定具有侧壁表面的空腔。 所述半导体器件组件还包括附接到邻近所述空腔的所述第一裸片的周边区域的热传递结构，以及至少部分地填充所述腔并且在所述外围区域和所述第二半导体管芯堆叠之间包括圆角的底部填充材料。

公开(公告)号：US20150348954A1

公开(公告)日：2015-12-03

申请号：US14287418

申请日：2014-05-27

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13565 ,  H01L2224/13647 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/17107 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83487 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01047

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Abstract translation: 本文公开了具有冗余电连接器的互连结构的半导体管芯组件。 在一个实施例中，半导体管芯组件包括第一半导体管芯，第二半导体管芯和第一和第二半导体管芯之间的互连结构。 互连结构包括耦合到第一半导体管芯的第一导电膜和耦合到第二半导体管芯的第二导电膜。 互连结构还包括在第一和第二导电膜之间延伸并经由第一导电膜彼此电耦合的多个冗余电连接器。

公开(公告)号：US11430809B2

公开(公告)日：2022-08-30

申请号：US16984457

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H01L27/11582 ,  G11C5/02 ,  H01L21/768 ,  G11C16/04 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.