公开(公告)号：US09641102B2

公开(公告)日：2017-05-02

申请号：US14941721

申请日：2015-11-16

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro Mitamura ,  Koji Bando ,  Yukihiro Sato ,  Takamitsu Kanazawa

IPC: H02M7/537 ,  H01L27/06 ,  H01L29/739 ,  H01L29/861 ,  H01L23/31 ,  H01L23/495 ,  H02M7/00 ,  H02P27/06 ,  H01L23/00

CPC classification number: H02M7/537 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/0781 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H02M7/003 ,  H02P27/06 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014

Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

公开(公告)号：US09576885B2

公开(公告)日：2017-02-21

申请号：US14863894

申请日：2015-09-24

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko Funatsu ,  Yukihiro Sato ,  Takamitsu Kanazawa ,  Masahiro Koido ,  Hiroyoshi Taya

IPC: H01L23/495 ,  H01L23/15 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L25/07

CPC classification number: H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

Abstract translation: 半导体器件包括形成在陶瓷衬底上的多个金属图案和安装在多个金属图案中的一些上的半导体芯片。 此外，在多个金属图案的周边部分中形成多个中空部分。 此外，多个中空部分不形成在与多个金属图案中的半导体芯片重叠的区域中。 此外，多个中空部分设置在多个金属图案中，多个金属图案布置在多个金属图案中最靠近陶瓷基板的顶表面的周边部分的位置。

公开(公告)号：US09478483B2

公开(公告)日：2016-10-25

申请号：US13764336

申请日：2013-02-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro Sato ,  Tomoaki Uno

IPC: H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H02M7/00

CPC classification number: H01L23/492 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Abstract translation: 提高了半导体器件的可靠性。 半导体器件的封装在内部包括形成功率MOS•FET的第一半导体芯片和第二半导体芯片，以及形成控制第一和第二半导体芯片的控制电路的第三半导体芯片。 第一至第三半导体芯片分别安装在芯片焊盘上。 第一半导体芯片的高侧的源电极接合焊盘通过金属板与管芯焊盘的第一管芯焊盘电连接。 在芯片焊盘7D2的顶面设置有形成在安装有第二半导体芯片的区域中的镀层和形成在金属板接合的区域中的另一个镀层，并且将镀层彼此分离，并且用 在其间不形成镀层的区域。

公开(公告)号：US09362238B2

公开(公告)日：2016-06-07

申请号：US14919597

申请日：2015-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko Funatsu ,  Yukihiro Sato ,  Yuichi Yato ,  Tomoaki Uno

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/564 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

公开(公告)号：US10141248B2

公开(公告)日：2018-11-27

申请号：US15385637

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Akira Muto ,  Koji Bando ,  Yukihiro Sato ,  Kazuhiro Mitamura

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31

Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

公开(公告)号：US10049968B2

公开(公告)日：2018-08-14

申请号：US15858493

申请日：2017-12-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro Sato ,  Akira Muto ,  Ryo Kanda ,  Takamitsu Kanazawa

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L27/06 ,  H01L29/739 ,  H01L25/075 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

公开(公告)号：US09343451B2

公开(公告)日：2016-05-17

申请号：US14685145

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yukihiro Sato

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/683 ,  H01L21/78 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

公开(公告)号：US20130256860A1

公开(公告)日：2013-10-03

申请号：US13771235

申请日：2013-02-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro Sato ,  Nobuya Koike

IPC: H01L23/495 ,  H01L21/58

CPC classification number: H01L21/561 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.