公开(公告)号：US09831156B2

公开(公告)日：2017-11-28

申请号：US15076141

申请日：2016-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L27/06 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05563 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08147 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.

公开(公告)号：US09768143B2

公开(公告)日：2017-09-19

申请号：US14488017

申请日：2014-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L24/82 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/80 ,  H01L27/0688 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80855 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/9202 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second conductive material embedded in a second polymer material. The first conductive material of the first semiconductor wafer bonded to the second conductive material of the second semiconductor wafer and the first polymer material of the first semiconductor wafer is bonded to the second polymer material of the second semiconductor wafer. The semiconductor device structure further includes at least one through substrate via (TSV) extending from a bottom surface of the second semiconductor wafer to a top surface of the first semiconductor wafer.

公开(公告)号：US20170103954A1

公开(公告)日：2017-04-13

申请号：US15389738

申请日：2016-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

公开(公告)号：US20160118372A1

公开(公告)日：2016-04-28

申请号：US14990012

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4875 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/02 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an interfacial layer over sidewalls and tops of the conductive columns. The method also includes disposing a semiconductor die over a planar portion of the interfacial layer. The method further includes forming a molding compound to partially or completely encapsulate the semiconductor die, the conductive columns, and the interfacial layer such that the molding compound is in direct contact with the interfacial layer.

Abstract translation: 提供一种形成封装结构的方法。 该方法包括在载体基底上形成多个导电柱，并在导电柱的侧壁和顶部上形成界面层。 该方法还包括在界面层的平面部分上设置半导体管芯。 该方法还包括形成模制化合物以部分或完全地包封半导体管芯，导电柱和界面层，使得模塑料与界面层直接接触。

公开(公告)号：US09087821B2

公开(公告)日：2015-07-21

申请号：US13943224

申请日：2013-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/89 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/08145 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/0002 ,  H01L2924/1304 ,  H01L2924/00

Abstract: Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV.

Abstract translation: 提供了形成半导体器件结构的实施例。 半导体器件结构包括通过混合键合结构接合的第一半导体晶片和第二半导体晶片，并且所述混合键合结构包括嵌入第一聚合物材料中的第一导电材料和嵌入第二聚合物材料中的第二导电材料。 第一导电材料结合到第二导电材料上，第一聚合物材料结合到第二聚合物材料上。 半导体器件还包括从第一半导体晶片的底表面延伸到第一半导体晶片的金属化结构的至少一个穿硅通孔（TSV）。 半导体器件结构还包括形成在第一半导体晶片的底表面上的互连结构，并且互连结构经由TSV与金属化结构电连接。

公开(公告)号：US20240096642A1

公开(公告)日：2024-03-21

申请号：US18523457

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L21/321 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L21/321 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76888 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/5329

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

公开(公告)号：US11901302B2

公开(公告)日：2024-02-13

申请号：US17360313

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/2919 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/18 ,  H01L2924/0001 ,  H01L2224/2919 ,  H01L2924/00014

Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

公开(公告)号：US11848247B2

公开(公告)日：2023-12-19

申请号：US17335588

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Shih-Yi Syu

IPC: H01L21/00 ,  H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/768 ,  H01L25/075

CPC classification number: H01L23/367 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/0756 ,  H01L2224/13 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

公开(公告)号：US11842936B2

公开(公告)日：2023-12-12

申请号：US17384923

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/0652

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US11776935B2

公开(公告)日：2023-10-03

申请号：US17853524

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/552 ,  H01L21/3205 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.