公开(公告)号：US20120091570A1

公开(公告)日：2012-04-19

申请号：US13166998

申请日：2011-06-23

申请人： YU TANG PAN ,  SHIH WEN CHOU

发明人： YU TANG PAN ,  SHIH WEN CHOU

IPC分类号： H01L23/495 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening.

摘要翻译： 芯片封装方法包括以下步骤：将第一带附接到金属板; 图案化金属板以形成多个端子焊盘和多个引线，其中多个端子焊盘和多个引线设置在中心空隙区域的两个相对侧上，每个侧面上的多个端子焊盘被布置 在离开中心空隙区域的方向上彼此隔开的至少两排，并且每个引线具有延伸到中心空隙区域的第一端部和连接到相应的端子焊盘的第二端部; 将具有开口的第二带附接到所述多个端子焊盘，其中每个所述开口暴露所述引线的中心空隙区域和所述第一端部; 去除第一个磁带; 将芯片附接到所述多个端子焊盘和所述多个引线，其中所述芯片上的多个接合焊盘对应于所述中心空隙区域; 以及通过所述开口将所述接合焊盘连接到所述引线的所述第一端部的多个接合线。

公开(公告)号：US20110291273A1

公开(公告)日：2011-12-01

申请号：US13104597

申请日：2011-05-10

申请人： CHENG TANG HUANG

发明人： CHENG TANG HUANG

IPC分类号： H01L23/488 ,  H01L21/283

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/10125 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/13566 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A chip bump structure is formed on a substrate. The substrate includes at least one contact pad and a dielectric layer. The dielectric layer has at least one opening. The at least one opening exposes the at least one contact pad. The chip bump structure includes at least one elastic bump, at least one first metal layer, at least one second metal layer, and at least one solder ball. The at least one elastic bump covers a central portion of the at least one contact pad. The at least one first metal layer covers the at least one elastic bump. The at least one first metal layer has a portion of the at least one contact pad. The portion of the at least one contact pad is not overlaid by the at least one elastic bump. The at least one second metal layer is formed on a portion of the at least one first metal layer. The portion of the at least one first metal layer is located on the top of the at least one elastic bump. The at least one solder ball is formed on the at least one second metal layer. The at least one solder ball is also on the top of the at least one elastic bump.

摘要翻译： 在基板上形成芯片凸块结构。 衬底包括至少一个接触焊盘和介电层。 电介质层具有至少一个开口。 所述至少一个开口暴露所述至少一个接触垫。 芯片凸块结构包括至少一个弹性凸块，至少一个第一金属层，至少一个第二金属层和至少一个焊球。 所述至少一个弹性凸块覆盖所述至少一个接触垫的中心部分。 所述至少一个第一金属层覆盖所述至少一个弹性凸块。 所述至少一个第一金属层具有所述至少一个接触垫的一部分。 至少一个接触垫的部分不被至少一个弹性凸块覆盖。 所述至少一个第二金属层形成在所述至少一个第一金属层的一部分上。 所述至少一个第一金属层的所述部分位于所述至少一个弹性凸块的顶部上。 所述至少一个焊球形成在所述至少一个第二金属层上。 所述至少一个焊球也位于所述至少一个弹性凸块的顶部。

公开(公告)号：US08058109B2

公开(公告)日：2011-11-15

申请号：US12899530

申请日：2010-10-06

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/00

CPC分类号： H01L23/49894 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/90 ,  H01L24/97 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor structure, —including—the following steps of: forming a substrate having a package array; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括以下步骤：形成具有封装阵列的衬底; 形成覆盖所述基板的热固性非导电层; 部分固化热固性非导电层以形成半固体非导电层; 将芯片连接到衬底上的封装阵列; 挤压和加热芯片和基板，使得半固体非导电层与芯片和基板粘合; 预热在金属层上预成型的密封剂; 用密封剂覆盖基板上的芯片; 并固化所述密封剂以完全覆盖所述基板上的所述芯片。 本发明可以减少金的使用以降低制造成本，并且还可以提高半导体结构的热传导效率，以提高芯片的操作稳定性。

公开(公告)号：US08026615B2

公开(公告)日：2011-09-27

申请号：US12825811

申请日：2010-06-29

申请人： Hung Tsun Lin ,  Wu Chang Tu ,  Cheng Ting Wu

发明人： Hung Tsun Lin ,  Wu Chang Tu ,  Cheng Ting Wu

IPC分类号： H01L23/49 ,  H05K1/11

CPC分类号： H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/585 ,  H01L24/28 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.

摘要翻译： IC封装主要包括芯片，多个电连接部件以及包括基板，管芯安装层和至少一个接合线的芯片载体。 衬底具有顶表面和底表面，其中顶表面包括用于与管芯附着层一起设置的管芯附接区域。 芯片通过管芯附着层附接到管芯附着区域，并通过电连接部件与衬底电连接。 接合线的两端分别与衬底的顶面上的两个互连指状物接合，并且至少一部分接合线被封装在管芯附着层中，使得形成在常规衬底上的一些布线或通孔为 不需要。 因此，基板可以具有更简单的结构和更少数量的布线层; 因此，可以降低基板成本。

公开(公告)号：US20110212615A1

公开(公告)日：2011-09-01

申请号：US13104980

申请日：2011-05-11

申请人： Cheng-Tang Huang

发明人： Cheng-Tang Huang

IPC分类号： H01L21/283

CPC分类号： H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1191 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface.

摘要翻译： 公开了一种具有加强件的凸块结构的制造方法。 首先，提供包括焊盘和钝化层的衬底。 钝化层具有第一开口，并且每个第一开口分别暴露相应衬垫的一部分。 接下来，在衬底上形成底部球金属（UBM）材料层以覆盖钝化层和由钝化层暴露的焊盘。 在UBM材料层上形成凸起，并且每个凸起的下表面小于开口的下表面。 形成在每个凸块周围的UBM材料层上的每个加强构件与每个凸块接触，并且加强构件的材料是聚合物。 将UBM材料层图案化以形成UBM层，并且每个UBM层的下表面大于每个相应开口的下表面。 因此，凸块具有平坦的上表面。

公开(公告)号：US20110207262A1

公开(公告)日：2011-08-25

申请号：US12899530

申请日：2010-10-06

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/603

CPC分类号： H01L23/49894 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/90 ,  H01L24/97 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括以下步骤：形成具有封装阵列的衬底，其中所述封装阵列具有多个接触焊盘和保护层，并且所述多个接触焊盘暴露于 保护层的外侧; 形成覆盖所述基板的热固性非导电层; 部分固化热固性非导电层以形成半固体非导电层; 将芯片连接到基板上的封装阵列，其中每个芯片具有活性表面，多个芯片焊盘和多个复合凸块，在有源表面上形成芯片焊盘，并且复合凸块形成在 芯片焊盘，使得复合凸块电连接到每个接触焊盘; 挤压和加热芯片和基板，使得半固体非导电层与芯片和基板粘合; 预热在金属层上预成型的密封剂; 用密封剂覆盖基板上的芯片; 并固化所述密封剂以完全覆盖所述基板上的所述芯片。 本发明可以减少金的使用以降低制造成本，并且还可以提高半导体结构的热传导效率，以提高芯片的操作稳定性。

公开(公告)号：US07960214B2

公开(公告)日：2011-06-14

申请号：US12169132

申请日：2008-07-08

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成多个凸点。 在第一基板上或第二基板上形成第一两级粘合剂层，并且被B阶段化以形成第一B阶粘合剂层。 在第一B阶粘合剂层上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一B阶粘合剂层和第二B阶粘合剂层接合，使得每个第一接合焊盘分别经由第一接合焊盘中的一个电连接到第二接合焊盘中的一个 颠簸

公开(公告)号：USRE42349E1

公开(公告)日：2011-05-10

申请号：US11371307

申请日：2006-03-07

申请人： Chun-Hung Lin ,  Jesse Huang ,  Kuang-Hui Chen ,  Shih-Wen Chou

发明人： Chun-Hung Lin ,  Jesse Huang ,  Kuang-Hui Chen ,  Shih-Wen Chou

IPC分类号： B05D5/10 ,  B05D3/12 ,  H01L21/00

CPC分类号： H01L24/27 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

摘要翻译： 提供了一种用于制造粘合剂模具的晶片处理方法。 具有两级特性的液体粘合剂涂覆在晶片的表面上。 然后，将晶片预固化，使液体粘合剂转变具有玻璃化转变温度不低于40℃的B阶特性的热粘合粘合剂膜，以在室温下无粘合剂进行处理。 在定位晶片之后，将晶片单片化以形成具有用于管芯到管芯堆叠，管芯到衬底或管芯到引线框架附接的粘合剂的多个管芯。

公开(公告)号：US07936032B2

公开(公告)日：2011-05-03

申请号：US11727200

申请日：2007-03-23

申请人： Ming-Liang Huang ,  Yao-Jung Lee ,  Ming-Hsun Li

发明人： Ming-Liang Huang ,  Yao-Jung Lee ,  Ming-Hsun Li

IPC分类号： H01L31/107

CPC分类号： G06K9/00026 ,  G06K9/00973 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

摘要： A thin-film fingerprint sensor package primarily comprises a fingerprint sensor chip, a plurality of bumps, a wiring film with a plurality of leads and at least an encapsulant to encapsulate the bumps. A sensing area is formed on an active surface of the fingerprint sensor chip. The bumps are disposed on the active surface and located at two opposing sides of the sensing area. The wiring film has an opening to expose the sensing area. Each lead has an inner end and an outer end. The inner ends are located at two opposing sides of the opening and are bonded to the bumps. Preferably, the wiring film has a flexible extension and the outer ends of the leads are rerouted to the extension for external electrical connections.

摘要翻译： 薄膜指纹传感器封装主要包括指纹传感器芯片，多个凸块，具有多个引线的布线膜和至少封装凸块的密封剂。 感测区域形成在指纹传感器芯片的有效表面上。 凸起设置在活动表面上并且位于感测区域的两个相对侧。 布线膜具有暴露感测区域的开口。 每个引线都有一个内端和一个外端。 内端位于开口的两个相对侧并且接合到凸起。 优选地，布线膜具有柔性延伸部分，并且引线的外端重新路由到用于外部电连接的延伸部分。

公开(公告)号：US07915690B2

公开(公告)日：2011-03-29

申请号：US12635388

申请日：2009-12-10

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2224/82

摘要： A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material.

摘要翻译： 提供了一种管芯重排封装结构，其包括具有活性表面和底表面的管芯，并且多个焊盘设置在有源表面上; 提供封装体以覆盖裸片并且所述有源表面被暴露; 提供具有至少一个狭缝的聚合物材料以覆盖有源表面，并且所述焊盘从所述狭缝暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖管芯的活性表面和每个金属迹线，并且金属迹线的另一端被暴露; 多个连接元件与金属迹线的另一端电连接，其特征在于：封装体是B级材料。